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In this paper, a TSMC 0.25-pm BCD process is used to evaluate the electrostatic discharge (ESD) protection robustness by modulating the cathode-side of an insetting SCR in the high-voltage (HV) p-channel lateral-diffused MOSFET (pLDMOS) device. The influences of ESD protection capability and latch-up (LU) immunity in these HV pLDMOS devices by the embedded SCR structures and cathode-side discrete...
For the anti-ESD reliability consideration, the drain-side with super-junction structures and “npn” embedded type SCRs of nLDMOS transistors are investigated in this paper. From the experimental data, we can find that the layout manner of super-junction types in the drain-side have positive impacts on the anti-ESD capability. On the other hand, as the drain-side added another item i.e. an embedded...
Repercussions on the reliability capability and electrical performance of power p-channel LDMOS devices by different discrete-distributed architectures in the drainside are investigated in this paper. Here, in order to effectively improve the reliability issues, a drain-side "NPN" and "PNP" styles of pLDMOS-SCR with some discrete-distributed areas arrangement are fabricated by...
This study reports the impacts of various drain end layouts on the reliability and electrical performance of 60-V p-channel laterally diffused metal–oxide-semiconductor (pLDMOS) FETs. For effectively improving the reliability, drain-end “N-P-N” and “P-N-P” permutated pLDMOSs embedded with silicon-controlled rectifiers (pLDMOS–SCRs) with discrete regulated structures in the drain strap were manufactured...
A pMOS transistor can be used as an electrostatic discharge (ESD) protection device; however, due to its higher turn-on resistance, it has a poor ESD robustness than that of nMOS transistors. Nevertheless, for a high-voltage (HV) p-channel laterally-diffused MOS (pLDMOS), which has a low impact-ionization rate, almost a non-snapback phenomenon (high Vh value) and then with a high latch-up (LU) immunity...
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