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We present industrial experience on software health monitoring. Our goal was to determine whether we can predict abnormal behavior, based on data captured from software system interfaces. To analyze the system state and predict software health problems, we used Support Vector Machine (SVM) based analysis. To train the SVM, we exploited random testing with feedback and swarm testing with feedback to...
We present a method for exploiting symmetry-breaking constraints in modular schemes for constructing equivalent Boolean encodings of cardinality constraints. These techniques result in speedup in automated debugging of complex VLIW processors in formal verification by Correspondence Checking and efficient translation to Boolean Satisfiability (SAT).
We study the efficient formal verification of polymorphic heterogeneous multi-core architectures, such as Bahurupi, and also present insights on how to design such architectures at a high level of abstraction in order to facilitates their formal verification. To the best of our knowledge, this is the first work on formal verification of such architectures.
We present highly automatic techniques for formal verification of pipelined microprocessors with hardware support for multithreading. The processors are modeled at a high level of abstraction, using a subset of Verilog, in a way that allows us to exploit the property of Positive Equality that results in significant simplifications of the solution space, and orders of magnitude speedup relative to...
With the number of processor cores in modern CPUs growing exponentially, it is expected that CPUs will have on the order of a hundred cores in the next 5 - 7 years. Thus, the need to implement parallel SMT decision procedures to utilize the increasing number of cores. We study a method to design independent strategies for a portfolio of parallel independent strategies in an SMT decision procedure...
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