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Asymmetric Error Reduction Huffman Coding (AERH) is proposed for MLC/3LC NAND flash memory used as SSD cache in the tiered hierarchical storage. AERH compresses data, reduces asymmetric memory cell errors by modulating Vth distribution and thus enhances reliability and endurance of memory cells. AERH decreases data-retention errors by 72.6% and 82.6% of MLC and 3LC NAND flash, respectively. In addition,...
Read-disturb characteristics in 1Ynm NAND flash memories have been investigated. The error regularity among word-lines is observed in 1Ynm (2nd generation below 20nm) triple-level cell (TLC) NAND flash. Consequently, unreliable page which exceeds error-correcting code (ECC) capability is occurred. To optimize ECC capability, system level solution with Bose-Chaudhuri-Hocquenghem (BCH) ECC is introduced...
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