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A 10-bit 2GS/s time-interleaved SAR ADC with low-complexity background timing skew calibration is presented. 10% of the area is utilized for the interleaving mismatch estimation and correction. The ADC achieves −64dB mismatch spur and 50.1dB SNDR at Nyquist rate, with 10.4mW power consumption and 0.014mm2 area in 16nm.
As the time of mobile Internet has come gently, the mobile applications has progressively designed by techniques based on web technology. The web technology has a lot of strong points such as highspeed developing, fast adapting, and so on. However, on the other hand, it has harsh requirements about the performance and cost of the application. This paper comes out with a strategy of advancing the mobile...
This paper is concerned with the design of a high speed current steering DAC. Techniques to improve static precision are preserved while their negative influences on dynamic performance are suppressed. The prototype is implemented with the SMIC 0.13 ??m process. With an update rate of 700 Msamples/s, measurements show that the DAC achieves over 40 dB SFDR under a sampling rate of 700 Ms/s and consumes...
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