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The concept of design-manufacturing collaboration for nano-lithography era has been clarified. The novel design-manufacturing system that the manufacturing tolerance reflecting design intention properly can be allocated to the layout has been proposed. According to the system, one can assign the “weak portion” explicitly on the layout, and can control the process for reducing the burden of manufacturing...
The dependence of the interface-trap-induced scattering on the electron kinetic energy (epsivele) in nMOSFETs is investigated experimentally. The procedure to extract the accurate epsivele dependence of the interface-trap-induced scattering relationship is developed based on the careful Hall effect measurements. As a result, it is demonstrated that as epsivele increases, the interface-trap-induced...
Extremely high density CMOS technology for 40 nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100 kGate/mm2 is realized by breaking down conventional trade-off of leakage power and performance with three key approaches. 0.195 mum2 SRAM with excellent static noise margin...
Random telegraph noise (RTN) in scaled FETs is one of the biggest concerns in the present and future LSIs. However, RTN in high-kappa gate dielectric FETs have not been fully studied yet. In this paper, we have studied RTN in high-kappa pFETs in comparison with that in SiO2 pFETs. It is found for the first time that the reduction of the RTN amplitude (DeltaId/Id) by the surface holes is smaller in...
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