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Two major trends can be observed in a modern system-on- chip design: first a growing trend in system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architectures. The second in technology scaling indicates that the wires are getting thinner and results in an increment of wire delay and power consumption. These, in turn, result in the degradation...
This paper presents a statistical approach to synthesize an energy conscious the optimal bus width and the number of buses. The slack is exploited to maximize bus sharing and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of on-chip communication bus. An assumption for bus synthesis is that a system has been partitioned and mapped onto the appropriate modules...
We propose a statistical approach for minimizing on-chip communication bus width and number of buses with reduced communication energy under timing yield constraint. The slack is exploited to maximize sharing of buses and to reduce energy by simultaneously scaling the voltage during the communication synthesis. Because of the diversity of applications to be run on a single SoC, there exists variability...
This paper presents an energy efficient on-chip communication synthesis for shared bus based architecture. An assumption for the synthesis is that a system has already been partitioned and mapped onto the appropriate modules of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. The problem of communication synthesis is modeled in NLP (nonlinear programming), which...
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