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The paper presents an extension of interleave pipeline PRET architecture. The main emphasize is made on obtaining deterministic, time predicable data and a program memory system which cooperates with the pipeline processor. The idea is to pass control of all IO operations to a special unit called MACU (Memory Access Control Unit). Thread State Controller (TSC), Dynamic Interleave Controller (DIC)...
The paper concerns design and modeling of real time systems with strong timing requirements. The problem is presented and analyzed on high level abstract models implemented in SystemC - a modern tool for electronic embedded systems design. The paper outlines advantages of transaction level modeling technique, which is very efficient for complex systems and well suited in SystemC environment. The authors...
The paper presents the microarchitecture of highly predictable real-time systems based on pipeline processor with the idea of thread interleaving. The abstract model of such to real-time electronic embedded systems is given. The authors put their main efforts to obtain highly repeatable and time predictable applications with strong timing requirements. The problem is presented and analyzed on high...
Tematem artykułu jest oryginalny algorytm umożliwiający wyznaczanie najmniejszych cykli fundamentalnych w grafie nieskierowanym. Zaprezentowane podejście wykorzystuje specyficzną reprezentację grafu w postaci trójkątnej macierzy sąsiedztwa. Na podstawie wyznaczonych cykli algorytm buduje drzewo grafu dodając kolejno wyznaczone w poprzednim kroku cykle. Zaprezentowano kolejne kroki algorytmu wraz z...
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