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This paper deals with the comparison of the analog and digital phase-locked loops that use identical LC VCO. Both circuits were designed and simulated in CMOS AMS 0.35 μm (3.3 V) technology using full-custom technique. The centre frequency of the oscillator is about 1.1 GHz. The analog loop consists of the Gilbert multiplying phase detector and active low-pass filter while digital one is built of...
This paper deals with the design and simulations of a 4-bit flash analog-to-digital asynchronous converter designed in 0.35 mum CMOS technology. The input voltage signals of a range of 1.6 V are converted to binary numbers based on flash method. Analog part of the project, which is made using full-custom technique, contains 17 comparators. The two extra comparators indicate when input signal is out...
This paper is devoted to investigations into static and dynamic energy consumption of digital CMOS VLSI systems. The analyses are performed for currently available technologies as well as the predictive ones and cover technologies from 32 nm to 3 mum. Next, the formula that describes the ratio of static versus dynamic parts of energy consumption is proposed and further analyses for technology scaling...
In this paper the temperature influence on quasi short-circuit component of energy consumption is investigated. This work takes into account values of zero temperature coefficient points related to supply voltage. The wide range of CMOS technology processes (from 32 nm to 3 μm) is considered.
AnaDig, an IC designed for educational purposes, is described. The teaching goal of the chip is to familiarize the students with the properties of IC devices and basic building blocks. Numerous laboratory experiments are available within the same measurement environment. The temperature dependent characteristics can be obtained. The chip was prototyped and verified.
The paper presents new supervisors dedicated to predictive methods of dynamic power management, i.e. DCT (dynamic clock throttling), DFS (dynamic frequency scaling), and DVS (dynamic voltage scaling). The presented supervisors make decisions on the basis of current chip temperature; future, current and previous power dissipations. They consist in cooperation with operating system and they are dedicated...
In this paper, we describe the parameters identification results of PTAT (proportional to absolute temperature) temperature sensors that are implemented in the test chip and dedicated to CMOS integrated circuits. Theirs principles of operation are based on the vertical PNP structure. These sensing elements are uniformly distributed on the chip surface. The chip is dedicated to analyses and verifications...
The paper presents techniques of dynamic control of digital integrated systems performance considering die temperature. The dynamic clock throttling (DCT) and the dynamic frequency scaling (DFS) are taken into account. Allowing for the power-time product (pt) a new predictive method that improves the efficiency of DCT and DFS techniques is introduced
The paper presents theoretical analyses, simulations and design of a PTAT (proportional to absolute temperature) temperature sensor that is based on the vertical PNP structure and dedicated to CMOS VLSI circuits. Performed considerations take into account specific properties of materials that forms electronic elements. The electrothermal simulations are performed in order to verify the unwanted self-heating...
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