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Sub-30 nm TFT CT NAND flash devices have been extensively studied. Although TFT devices were often believed to have much worse performance than bulk devices, our results show that as devices scale down to sub-30 nm, the DC characteristics (such as read current and subthreshold slope (S.S.)) approach those of the bulk devices because sub-30 nm TFT devices often contain no grain boundaries. The memory...
Floating gate (FG) devices using barrier-engineered (BE) tunneling dielectric have been studied both theoretically and experimentally. Through WKB modeling the tunneling efficiency of various multi-layer tunneling barriers can be well predicted. Experimental results for FG devices with oxide-nitride-oxide (ONO) U-shaped barrier are examined to validate our model. Furthermore, a 1Mb test chip was fabricated...
The interference and fringing field effects beyond sub-30 nm node charge-trapping(CT) NAND Flash are studied critically using 3D simulation. Due to the relatively large EOT (>15 nm) compared to the device dimension (F), the most severe interference comes from adjacent pass-gate WL bias disturb through the edge fringing field effect. On the other hand, the program charges in adjacent devices generate...
In NAND flash, devices are normally erased to negative Vt and then programmed to positive Vt. In this work we introduce a novel depletion-mode (normally on) buried-channel, junction-free n-channel NAND flash device. The buried-channel NAND flash shifts the P/E Vt ranges below those for the conventional surface-channel device, and is more suitable for the NAND Flash memory design. Due to the lower...
We have successfully demonstrated a novel junction-free BE-SONOS NAND Flash. Junction-free devices greatly improve the short channel effect and thus promise scaling of NAND Flash below 20 nm node. Instead of S/D junctions a very small space (Lt 30 nm) is left between adjacent devices. Junction is formed only at the outer region of NAND array, while there is no junction inside the array. Fringe field...
Incremental-step-pulse programming (ISPP) is a key enabler for achieving tight VT distribution for MLC NAND Flash. The ISPP characteristics for BE-SONOS NAND Flash are studied extensively in this work. Experimentally we find that the ISPP slope is very close to 1 for BE-SONOS capacitors for a wide range of EOT and O1 variations. A theoretical model is developed to prove that ISPP slope~1 is a universal...
Summary form only given. Flash memories have provided reliable solid-state storage solutions for over twenty years. In the last few years we have seen an explosive growth of NAND flash, fueled by digital camera, USB, MP3, iPhone and numerous new mobile applications. However, this phenomenal boom is silently threatened by scaling limitations intrinsically built into the flash devices. Old challenges...
We present a new memory device using two self-aligned silicon wires for charge storage. Programming is by channel hot electron injection, and a large 2nd bit VT window ( >3 V) for multi-bit/cell operation is demonstrated. Erasing is by edge-enhanced +FN tunneling. Both program and erase operations can be performed at < 10 mus and the device is intrinsically immune to over-erasure. This new Si-wire...
A bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005) using Al2O3 top blocking layer and metal gate (MA BE-SONOS) is proposed to provide very fast erase speed without erase saturation. Compared with MANOS (Shin et al., 2005) using a thick (4.5 nm) tunnel oxide, MA BE-SONOS shows dramatically faster erase speed, owing to the help of bandgap engineered ONO barrier that facilitates hole tunneling...
The gate-sensing and channel-sensing transient analysis method is studied in detail. This method introduces an additional gate-sensing capacitor to be compared with the conventional channel-sensing one. Sensing in both modes provides two equations that are suitable to solve for two variables-the charge density (Q ) and the average charge vertical location (x ). In this paper, the principle of this...
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