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This paper presents an industrial case study on logic diagnosis targeting system-on-chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on the effect-cause paradigm. This approach consists of two phases: (i) a fault localization phase resorting to the critical path tracing to determine a set of suspects, (ii) a fault model...
IEEE 1500 is a standard under development which intends to improve ease of test reuse and test integration with respect to the core-based SoCs. The subject paper proposes developing test environment and test methodologies for digital embedded cores based system-on-a-chip (SoC). The digital cores used in the study were constructed from ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits...
Increasing power densities due to process scaling, combined with high switching activity and poor cooling environments during testing, have the potential to result in high integrated circuit (IC) temperatures. This has the potential to damage ICs and cause good ICs to be discarded due to temperature-induced timing faults. We first study the power impact of scan chain testing for the ISCAS89 benchmarks...
Concurrent testing of the cores in a core-based system- on-chip reduces the test application time but increases the test power consumption. Power models, test architecture design, and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated...
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