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This paper presents a half-duplex pseudo-LVDS (low voltage differential signaling) transceiver for low-power high-speed interface system. The data rate of 6Gbps/pin and output data window of 147ps pk-pk was demonstrated using a 1.6GHz clock and 196mV swing. The power consumed by the only I/O circuit was measured to be 4.2mW/pin, when connected to a 10pF load, at a 1.2V output supply voltage. The transmitter...
This paper presents a high-speed LVDS I/O interface for mobile DRAMs. A data rate of 6Gbps/pin and a transmit-jitter of 57.31ps pk-pk were demonstrated, in which an 800MHz clock and a 200mV swing were used. The power consumption by I/O circuit is 6.2mW/pin when a 10pf load is connected to the I/O, and output supply voltage is 1.2V. The proposed mobile DRAM has 6 data pins and 4 address/command pins...
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