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In this paper, a novel adaptable reference circuit is proposed which can be used to calibrate the switching threshold of a read amplifier. The circuit is based on a network of nanoelectronic resistive switches acting as voltage dividers. In addition, active CMOS circuits are included which are used to tune the output voltage of the circuit. For the performance analysis variability models were applied...
QR decomposition accelerators are attractive SoC components for many applications. A new linear QRD array is proposed based on the Givens-algorithm and CORDIC (Coordinate Rotate Digital Computer) rotations. In order to achieve high area- and energy-efficiency a systematic design space exploration has to be applied. Thereby the strong interactions between the architecture, micro-architecture and circuit...
Conductance variations in nanoelectronic resistive switches seriously affect the performance of hybrid CMOS/memristive circuits. In order to capture cycle-to-cycle variability by circuit simulation a standard model was extended for resistive switches based on the electrochemical metallization effect. The extension incorporates an additional process that simulates the randomness of the filament growth...
Today, high-performance divider implementations almost always use the classical SRT algorithm in conjunction with a redundant residual representation like carry-save. In this paper, a modified approach is presented, which reduces the number of comparisons inside the quotient digit selection function (QDSF) to the number necessary in a non-redundant implementation of the same radix. To keep the overlap...
Power dissipation has become one of the most critical CMOS design parameters. It will be shown that even under constraints on the supply voltage there are effective strategies for the reduction of power dissipation on the different levels of the CMOS design process. Enforcing localization, using redundant number representations and applying an optimal degree of pipelining will be demonstrated as the...
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