The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A new linearity improvement technique for a CMOS active resistor will be presented. In order to minimize the silicon area, an original method based on an optimal implementation of the current-controlled voltage generator will be proposed. The circuit is implemented in 0.35μm CMOS technology on a die area of 25μm × 40μm, being supplied at ± 3.6V. The active resistor presents a very good linearity (THD...
A new linearity improvement technique for a CMOS active resistor will be presented, using an anti-parallel connection of two quasi-identical active resistor structures, different biased and opposite excited. The second-order effects that affect the MOS transistor operation will be also taking into account, the proposed linearization method compensating also the linearity degradation imposed by these...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.