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The thermal resistance of a three-dimensional (3D) chip stack has been experimentally clarified by authors [1-5] and an additional cooling solution is strongly required to achieve various structures of 3D chip stacks. Especially, when a high heat dissipating chip is located as a bottom chip, cooling from the bottom side of chips (in other words, from the laminate (substrate) side) is identified to...
When a 3D chip stack is composed of some memories and a logic device such as processor, the logic device has been assumed to be located as a bottom chip in wide I/O and HBM applications. On the other hand, for high-end server applications, a processor needs to be located as a top chip because it needs to be cooled efficiently. In this case, many Through Silicon Vias (TSVs) are necessary in a memory...
For the thermal management of a three-dimensional (3D) chip stack, cooling from the bottom side of chips (in other words, from the laminate (substrate) side of chips), in addition to conventional cooling from the top surface of chips, is proposed. For cooling from the bottom side of chips, it is essential to consider the trade off among thermal, electrical and mechanical performance. Firstly, the...
To propose an appropriate cooling solution for a three-dimensional (3D) chip stack at the design phase, it is necessary to estimate the total thermal resistance of a 3D chip stack. The interconnection between stacked chips is considered as one of the thermal resistance bottleneck of a 3D chip stack, but it is not experimentally clear yet. We have previously measured the thermal conductivity of SnAg...
Three-dimensional (3D) chip stacks are receiving more attention for system performance enhancements. However, because of the higher circuit density, the cooling of 3D chip stacks gets more challenging. In conventional cooling methods, a heat sink or a micro-channel cooler is located at the top of the chip to dissipate the generated heat in a chip. In this paper, possible cooling methods from the bottom...
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