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One emerging trend of implementing phase locked loop (PLL) based frequency synthesizers is to leverage digital signal processing in the loop filtering for more flexibility, scalability and smaller silicon area. This paper examines the pros and cons of such digital-intensive PLL architecture, and discusses techniques to minimize its overhead in terms of implementation cost and performance degradation...
IP reuse methodology has been used extensively in SoC (System on Chip) design. In this reuse methodology, while design and implementation cost is saved, manufacturing cost is not. To further reduce the cost, this reuse concept has been proposed at mask and die level in three-dimension integrated circuit (3D IC). In order to achieve manufacturing reuse, in this paper, we propose a new methodology to...
A near-/sub-threshold programmable clock generator is proposed in this paper. The major challenge of the ultra-low voltage (ULV) circuits is that the lock-in range of the delay line is easily affected by the environmental variations. In the proposed clock generator, there is a PVT compensation unit which consists of a set of delay line and a PVT detector. The unit is responsible for adjusting the...
The concept of merging some 1-bit flip-flops into a multi-bit flip-flop is applied to reduce dynamic clock power and decrease the total flip-flop area in a synchronous design. To acquire these advantages, the design must be guaranteed to satisfy certain physical constraints in the merging process. In this paper, given a set of 1-bit flip-flops with the input and output timing constraints, the area...
Conversion from dc to the 10th Nyquist band is enabled in a SHA-less, 10-b, 100-MS/s pipelined ADC by digitally calibrating the clock skew in the 3.5-b front-end stage. Architectural redundancy of pipelined ADC is exploited to extract skew information from the first-stage residue output with two out-of-range comparators and some simple digital logic; a gradient-descent algorithm is used to adaptively...
As the clock frequency increases, signal propagation delays on PCBs are requested to meet the timing specifications with very high accuracy. Generally speaking, the length controllability of a net decides the routing delay of the net. If a routing result has the higher length controllability, the routing delay will be obtained with higher accuracy. In this paper, given a start terminal, S, and a target...
The LSVN (limitation of the scope of visited nodes) problem is defined, which is caused by the scope limitation of visited nodes in Grid environment. It is found that at least one third nodes in grid are not visited. Problems caused by LSVN such as network bottleneck and service delay are studied. This paper proposes three strategies based on historical information to solve the LSVN problem and promote...
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