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An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.
In this paper, Sources of power consumption for CMOS logical circuits are analyzed and several BIST technologies of low power consumption are summarized. In order to reduce the switching activity rate of internal nodes in circuit-under-test and raise the correlation between testing vector, the Random Single Input Change (RSIC)test theory is introduced. It can reduce the switching activity rate of...
A fully differential 60 GHz three-stage transformer-coupled amplifier is designed and implemented in 65 nm digital CMOS process. On-chip transformers which offer DC biasing for individual stages, extra stabilization mechanisms, and simultaneous input/inter-stage/output matching networks are used to facilitate a compact circuit design. With a cascoded circuit configuration, the amplifier is tested...
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