The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
ReRAM (Resistive Random Access Memory) is an emerging non-volatile memory technology that exhibits high cell density and low standby power. ReRAM crossbars, while having the smallest 4F2 cell size, suffer from large sneak leakage, which not only wastes dynamic energy but also degrades system performance significantly. In this paper, we propose V-ReRAM, a novel ReRAM crossbar design based on 1TnR cell...
Energy consumption is an increasingly important issue for profit-driven cloud. Meanwhile, meeting users' expected response time is crucial for the real-time tasks. However, minimizing energy consumption may delay response time during task scheduling. Unfortunately, existing scheduling algorithms remain limit in balancing energy-saving and performance in elastic cloud environment. In view of this challenge,...
Phase change memory (PCM) has emerged as a promising non-volatile memory technology. Multi-level cell (MLC) PCM, while effectively reducing per bit fabrication cost, suffers from resistance drift based soft errors. It is challenging to construct reliable MLC chips that achieve high performance, high storage density, and low energy consumption simultaneously. In this paper, we propose ReadDuo, a fast...
Domain wall memory (DWM) is an emerging memory technology that utilizes magnetic domains along a nanowire to achieve high density, short latency and low power. Recent studies showed that it is promising to replace SRAM and STT-MRAM to construct DWM based on-chip caches. However, accessing DWM requires frequent shift operations, which leads to large energy consumption for DWM caches. In this paper,...
Nowadays, manufacturing enterprises consumes a significant amount of energy; consequently, it has a significant potential to reduce resource consumption. However, key performance indicators of the traditional production do not completely take into account environmental impacts like energy consumption in production planning and scheduling. Against this background, an energy-aware scheduling model for...
MLC STT-MRAM (Multi-level Cell Spin-Transfer Torque Magnetic RAM), an emerging non-volatile memory technology, has become a promising candidate to construct L2 caches for high-end embedded processors. However, the long write latency limits the effectiveness of MLC STT-MRAM based L2 caches. In this paper, we address this limitation with two novel designs: Line Pairing (LP) and Line Swapping (LS). LP...
An energy-balancing, cross-layer data gathering protocol (EB-CLDG) for wireless sensor networks (WSNs) is presented in this paper. EB-CLDG is proposed for monitoring and periodic reporting applications and the network is organized into concentric tiers around the sink. An energy-balancing clustering algorithm is employed to mitigate the ldquohot spotrdquo problem. Thus the number of clusters closer...
With the quick development in the application design of sensor networks, appropriate middleware, which provides efficient service for concurrent applications taking account into the scarce resources and sensor energy, is needed, which provides efficient service for concurrent applications taking account into the scarce resources and sensor energy. In this paper, we propose a novel message oriented...
Caches contribute to much of a microprocessor system's power and energy consumption. We have developed a new cache architecture, called a way-halting cache, that reduces energy while imposing no performance overhead. Our way-halting cache is a four-way set-associative cache that stores the four lowest-order bits of all ways' tags into a fully associative memory, which we call the halt tag array. The...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.