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The performance requirements of next-generation CMOS image sensors (CIS) have been increasing in terms of frame rate, read noise, dynamic range, as well as pixel resolution. In order to satisfy strict specifications, a column-parallel ADC is a key element in a state-of-the-art CIS. However, this architecture leads to side-effects such as vertical fixed pattern noise (VFPN) and read noise. In order...
This paper presents a CMOS image sensor integrating a 14b column-parallel cyclic ADC with on-chip digital error correction circuits. Column-parallel ADC arrays are located both above and below the pixel array. The area of the on-chip error-correction logic including memories for all the error coefficients of the 640 ADC channels is 0.85mmx7.9mm.
An ultra wide dynamic range image sensor with a linear response is presented. The proposed extremely short accumulation (ESA) signal readout technique enables the dynamic range of image sensor to be expanded up to 142dB. Including the ESA signals, total of 4 different accumulation time signals are read out in one frame based on burst readout mode. To achieve the high-speed readout required for the...
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