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The neural network model of computation has been proven to be faster and more energy-efficient than Boolean CMOS computations in numerous real-world applications. As a result, neuromorphic circuits have been garnering growing interest as the integration complexity within chips has reached several billion transistors. This article presents a digital implementation of a re-scalable spiking neural network...
Traditional IC design methodology based on standard cells shows its limitation on design efficiency, which can not satisfy the needs for shorter time-to-market and more advanced functionality of IC products. To solve this problem, a novel high level synthesis method named operator design method is proposed. In this paper, a scheduling scheme to timing optimization for operator design method is proposed,...
A fully-integrated programmable interference canceller is presented for the cognitive radio RF front-end, which is based on a double-loop cancellation technique. For a frequency division duplexing system (FDD), this interference canceller can suppress the Tx leakage and its associated noise at the Rx band. A negative delay line and a positive delay line are required for the double cancellation paths...
A prototype microsystem is presented for wireless neural recording application. An inductive link was built for transcutaneous wireless power transfer and data transmission. Total 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1-5 MHz with a distance of 0-10 mm. The integrated amplifiers were designed with a limited bandwidth for neural signals acquisition. The gain of 60 dB...
An LC injection locked frequency divider (ILFD) in CMOS technology is designed. By adopting the direct injection of signal into the resonation tank, the locking range of the ILFD is improved. For the purpose of reducing the power consumption, the complimentary topology is adopted in this work and also the voltage swing of the ILFD is optimized. The simulation results indicate that the ILFD has a wide...
A prototype neuro-stimulus chip for sub-retinal implants in blind patients affected by age-related macular degeneration (AMD) or retinitis pigmentosa (RP) is presented in this paper. This retinal prosthetic chip was designed to replace the degenerated photoreceptor cells, and in order to stimulate directly the remaining healthy layers of retinal neurons. The current stimulus circuits are monolithic...
A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated with standard 0.35 ??m CMOS technology. This OEIC circuit consists of light emitting diodes (LED), silicon dioxide waveguide, photodiodes and receiver circuit. The silicon LED operates in reverse breakdown mode and can be turned on at 8.5 V 10 mA. The silicon dioxide waveguide is composed of multiple layers...
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