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We suggested the heterogeneously stacked oxide (HSO) for the future tunnel oxide of high density NAND flash memory. HSO has a structure of SiO2/a-Si/a-SiOx using the concept of tunnel barrier engineering. By employing HSO tunnel barrier, it was possible to fabricate the tunnel oxide, which is thicker physically and thinner electrically than the single layer tunnel oxide. The bandgap of a-SiOx can...
The improvement of device performances has been achieved successfully through OAO IPD EOT scaling, which shows that OAO IPD is applicable to sub-40nm devices which require aggressive scaling of IPD EOT. Charge loss of OAO IPD at high temperature is explained by thermionic emission of alumina traps. Trap profiles of alumina were obtained by monitoring Vth shift above 100°C. OAO IPD shows good data...
We investigated threshold voltage shifts after program pulse in charge trap flash memory by measuring drain current changes. We have found threshold voltage shifts can be characterized as a function of not only the materials of tunnel oxide, trap layer, blocking layer, but also physical parameters like device size and electrical measurement environment such as program voltage target and gate bias...
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