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In this study, the charge pump (CP) was designed by gain-boosting amplifiers for lower mismatching. In this design two differential amplifiers were employed to reduce the effect of the channel length modulation in the transistors. This circuit was implemented by the 0.18-μm CMOS technology of TSMC at a power supply of 1.8 V. In our study, the measured mismatch was less than 1% for the output from...
We propose an asynchronous-logic (async) Quasi-Delay-Insensitive (QDI) Static Logic Transistor-level Implementation (SLTI) approach for low power sub-threshold operation. The approach is implemented to design 32-bit pipelined Arithmetic and Logic Units (ALUs), the primary computation core for microprocessors, and benchmarked against the reported Pre-Charged Half-Buffer (PCHB). There are two key attributes...
Novel self-timing switch-driving registers for high-speed successive approximation register (SAR) ADC is proposed. This circuit can provide fast charging path from comparator output to DAC array of SAR ADC and store the comparison results simultaneously at each approximation bit-cycle. The propagation delay from input to output of the register is about 60 ps only in a 90 nm CMOS process. By using...
IR drop noise has become a critical issue in advanced process technologies. Traditionally, timing analysis in which the IR drop noise is considered assumes a worst-case IR drop for each gate; however, using this assumption provides unduly pessimistic results. In this paper, we describe a timing analysis approach for power gating designs. To improve the accuracy of the gate delay calculation we determine...
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