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We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using...
History effects in 65-nm partially-depleted silicon-on-insulator CMOS technology are systematically measured and characterized. The impact of various process adjustments on these effects is analyzed, and an optimization strategy is presented. Hardware data show >9% history effect changes is controllable with no loss of performance (e.g. speed and leakage), offering more flexibility in SOI circuit...
A 10 Gb/s burst-mode CDR (clock and data recovery) IC, that is eight times faster than previous burst-mode ICs, is fabricated in a 0.13 /spl mu/m CMOS process. It amplifies an AC-coupled input burst by means of an edge detection technique, and extracts a clock within 5 UIs with a gated oscillator. It consumes 1.2 W from a 2.5 V supply.
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