The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The successfulness of wind energy is, its cost competitiveness, environmental clean, safeness and most importantly, it is a renewable energy. The Non linear control algorithms are used to maximize the system performance and optimize the control of wind turbine speed. This paper proposes wind speed estimation based neuro-fuzzy control to extract maximum power from the wind electrical power generating...
Emission control is one of the biggest challenge in today's automotive industry. Emission control can be achieved either by controlling combustion or by treating the exhaust gas. The latter is comparatively easier since there is less or no need to modify the engine itself. One such after treatment method is the use of catalytic converter. But, the 3-way converter is expensive due to use of both platinum...
In this paper we discuss different Subtracters design based on quantum dot cellular automata (QCA). QCA is an emerging nanotechnology for electronic circuits. It has the potential for attractive features such as faster speed, smaller size and low power consumption than transistor based technology. By taking the advantages of QCA we are able to design interesting computational architectures. The Subtracters:...
We describe the development and use of various test structures for 32 nm yield enhancement. These DC defect test structures are tested in parallel mode on a functional tester using special V/I and Pico-Amp measurement cards. This new test method provides measurement accuracy as high as plusmn10 pA along with up to 9times reduction in test time over conventional parametric testing. The large critical...
A comprehensive 45 nm short-flow test chip was designed and is currently used to improve defect-limited yield. In a novel development to reduce test time, the DC test structures are tested in parallel mode on a functional test platform, resulting in a 5x reduction in test time over conventional parametric testing. The large critical area enables accurate measurement of defect densities down to the...
This paper describes a yield learning infrastructure that has been developed and deployed to help rapidly ramp 65-nm random and systematic yield. This infrastructure consists of a 4-Mb addressable-array test circuit with >8000 unique test structures along with customized software and automated analysis routines to distill the large datasets generated. Examples of the successful application of this...
In this paper we report on the development and use of two scribe-line compatible addressable array test structures in 65 nm technology for routine process window monitoring. One array was dedicated for front-end of line test structures, while a second consists exclusively of back-end test structures. Fast testing allows large-scale sampling of wafer lots in a manufacturing environment. Customized...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.