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We present a novel SIMD multiply array for fixed-point and floating-point multiplication. To be concrete, the array supports one 54 (unsigned), one 32 or four 16 bits (signed/unsigned) operation. Based on the enhanced booth decode algorithm, the time overhead of the multiplications is reduced. The proposed intermediate result reuse strategy can reduce area overhead of the SIMD multiply array. The...
In deep nanometer scale, Network-on-Chip (NoC) links are more prone to multi-bit transient fault. Conventional ECC techniques brings heavy area, power, and timing overheads when correcting and detecting multiple transient faults. Therefore, a cost-effective ECC technique, named 2D fault coding method, is adopted to overcome the multi-bit transient fault issue of NoC links. Its key innovation is that...
The emergence of large-scale chip multicore processors makes the on-chip parallel H.264/AVC encoder with high parallelism feasible. To reduce the data reload frequency, a hierarchical chip multi-core DSP platform with overall 64 DSP cores is designed to accommodate the computation/data-intensive H.264/AVC encoder. To increase parallelism, macro block level parallelism is exploited in this paper and...
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