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This article proposed chip antenna and low noise amplifier with band pass filter for wearable and biomedical design has been successfully implemented. This integrated analog chipset has setup near-infrared laser-driven (NIRLD) might be a promising wireless electrical power source and phase in wake up receiver technology using direct active RF detection for biomedical nano-devices power saving.
A full-load low-dropout regulator (LDO) based on proposed hybrid compensation structure is proposed. The proposed LDO makes use of an NMOSFET power transistor. The LDO is able to be stabilized for 0 to 1-μF capacitive load. Experimental results prove the LDO stability and fast recovery speed.
In this paper, we have explored the impact of different gate architectures in controlling short channel effects in scaled AlGaN/GaN HEMT devices using calibrated 2-D TCAD simulations. Devices with different gate topologies, namely I-Gate and T-Gate are investigated for their efficacy in minimizing the short channel effects. Various parameters like transconductance, channel conductance and drain induced...
The design of a four-stage common-source (CS) 150 GHz amplifier in a 65nm technology is described. Each stage bases on the proposed technique of coupled transmission line (T-line) neutralization to achieve an improved intrinsic gain. Coupled T-line is also used for impedance matching, including both input and output, and inter stage impedance matching. Simulations show that the proposed amplifier...
The application of shallow trench isolation (STI) as trench capacitor is proposed in CMOS image sensor (CIS) to provide variable conversion gain. This provides higher sensitivity without degrading the dynamic range (DR) of the pixel. The proposed structure uses in-built isolation trenches as capacitors. In case of low light, trench capacitor (TC) is disconnected from the floating diffusion (FD) node...
We present a type of high performance contact-separation mode triboelectric generators (TEG). The TEGs consist of a poly(vinylidene fluoride) composite with embedded barium titanate nanomaterial (PVDF-BaTiO3) and polyamide-6 (PA6). Additional BaTiO3 nanomaterial in the PVDF increase the relative permittivity and piezoelectric effect, thus enhance the performance of the TEGs. Owing to the increased...
This paper presents a simulation study to achieve wide-linear-range transconductance of T-gate GaN HEMTs by introducing a δ-doped layer and a p-GaN back barrier. With optimized δ-doping density and location, the transconductance (gm) and current gain cutoff frequencies (fT) are ultra-flat and remain close to their peak values over a wide range of gate-source voltages (Vgs). In addition, a smaller...
In this paper, we propose two different hardware structure of SHA-3 hash algorithm for different width of circuit interface. They both support the four functions SHA3-224/256/384/512 of SHA-3 algorithm. The padding unit of our design is also implemented by hardware instead of software. Besides, a 3-round-in-1 structure is proposed to speed up the throughput of our circuit. We conduct an implementation...
Due to its potential applications in optoelectric area, WS2/graphene heterojunction attracts much attention in past years. But until now, modulation of their working performance is still a big challenge for the researchers. In this work, WS2/graphene heterojunctions have been sucessfully fabricated on Si substrate. Moreover, their surface configuration were researched by STM and AFM techniques. Finally,...
Various thicknesses (0, 5 and 70 nm) TiO2:Nb (TNO) films are used for the fabrication of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) with Mo/TNO source-drain (S-D) electrodes. All the as-prepared TFTs show similar electrical performance. However, the on-current of a-IGZO TFT with Mo/TNO(5 nm) S-D electrodes decreases dramatically after 300 °C annealing due to the large S-D parasitic resistance...
This paper proposes an automatic debugging method for single-electron transistor arrays. The method iteratively calls a SAT solver to find a counterexample and identify errors based on the counterexample. It can fix an incorrect SET array which can be corrected by changing an edge's configuration. The experimental results show that the proposed debugging method is efficient and effective. It finds...
This letter proposes a three-resonance CMOS LC-tank implant locked frequency multiplier (ILFM) fabricated in the 0.18 μm CMOS process and describes the circuit design, operation principle and measurement results of the ILFM. The ILFM circuit is composed of a RLC three-resonance first-harmonic implant-locked oscillator (ILO), a board-band frequency multiplier with differential-injection ports. The...
Study of electron transport in nanopillar transistor at 300K shows that elastic vibration is an intrinsic behavior of the device. The frequency observed in the drain-source current is found to agree with the charging frequency. Given a quantum dot of size 10×10×9nm3, the maximum displacement is estimated to be 0.3nm. Once the displacement diminishes to zero, single-electron tunnel becomes the dominating...
In this paper, an automatic parameter extraction and scalable modeling method for 1∼100GHz transmission line based on the equivalent-circuit model proposed in [1] is established. The parameters are extracted from electromagnetic simulations which are validated by the measurement date of the devices fabricated on HLMC 40nm RF CMOS process. This method is validated by application to scalable modeling...
Based on a 30-um-thick N-type epitaxial layer doped at 3 × 1015 cm−3, PiN diodes with etched junction termination extension (JTE) with floating guard rings (E-JFs) structure were designed and fabricated. Both the anode mesa and the JTE region were formed by ion implantation at 500°C and etching process. The measurement results show that the fabricated PiN diodes can block reverse voltage of 3.6 kV...
This paper presents a highly linear 28-GHz band SOI CMOS power amplifier with an adaptive bias circuit for cascode MOSFET for next generation wireless communication. The power amplifier consists of a cascode MOSFET, the adaptive bias circuit and the input and output matching circuits. The power amplifier has exhibited a simulated output P1dB (1-dB gain compression point) of 19.2 dBm and a PAE of 39...
In this work, we present a novel bit-cell which improves data stability in subthreshold SRAM operation. It consists of eight transistors, two of which cut off a positive feedback of cross-coupled inverters during the read access. In addition, the bit-cell keeps the noise-vulnerable data ‘low’ node voltage close to the ground level during the dummy-read operation, and thus producing near-ideal voltage...
In this paper, we evaluate the distributed deembedding methods in comparison with open-short deembedding technique for CMOS transistor on wafer characterization up to 40GHz. A set of NMOS transistor test structures fabricated on HLMC 40nm RF CMOS process are used for the investigation. Experimental results show the distributed methods are more physically reasonable than open-short deembedding technique...
This paper proposed the architecture of a linear current-mode CMOS image sensor integrated parallel processing unit enabling various block-level calculation during the read-out procedure. Combinational logic with two scanning DFF chains and global control signals as input generates the output to address the right pixels with high flexibility. Four current conveyors are used to perform CDS function...
In this study, ultrasonic treatment is involved in making the dye layer of proposed mercurochrome dye sensitized solar cells. The optimal conversion efficiency of the cells is about 1.03%.
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