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For many decades the semiconductor industry has enjoyed the benefits of scaling. Every 2 years or so a new process node would arrive, bringing with it reduced area, along with improved performance and power. In recent years, we have seen and overcome many challenges to the scaling model, necessitating considerable efforts in VLSI circuits and technology. While we have largely maintained area scaling,...
We investigate the mechanism of interfacial layer formation on Si1−xGex (0 < x < 0.5) channel and its correlation to hole mobility. It is found that the mobility degradation in low-Ge-content Si1−xGex (x < 0.2) pFETs is attributed to a Ge-rich top surface in the channel directly induced by interfacial layer formation. In addition, the depth profile of a Si-rich top surface in high-Ge-content...
We present a CMOS image sensor (CIS) with phase detection auto-focus (PDAF) in all pixels. The size of photodiode (PD) is 0.64μm by 1.28μm, the smallest ever reported and two PDs compose a single pixel. Inter PD isolation was fabricated by deep trench isolation (DTI) process in order to obtain an accurate AF performance. The layout and depth of DTI was optimized in order to eliminate side effects...
RESET distribution of phase-change random access memory (PRAM) is highly related to heat fluctuations during RESET write (RESETW). In this work we investigate the effect of load resistance (RL) with constant voltage write method and propose new RESETW method with an optimal RL selection equation with considering Joule heating and thermoelectric effects. Since the optimal RL compensates for intrinsic...
We demonstrated an integration of enhancement-mode single-crystalline n-channel thin-film transistor (TFT) and n+/p diodes for light detection/emission based on the single-crystalline GeSn alloy grown on a transparent substrate. Owing to the excellent crystal quality of GeSn layer and a high-quality n+/p junction, a record-high electron mobility of 271 cm2/Vs and a room-temperature near-infrared electroluminescence...
We report that the bandgap of 2D few layer black phosphorus (BP) can be electrically tuned by applying a perpendicular electric/displacement field. The variation of bandgap is as large as 200 meV with 2V/nm displacement field. The bandgap modulation can be understood with the quantum confined stark effect within the SiO2/BP/boron nitride (BN) sandwiched structure. This unique material property provides...
1D and 2D nanomaterials continue to show promise for use in electronic devices. Their atomically thin size and superb transport properties make them of great value for transistors scaled in size and, more importantly, in voltage. Meanwhile, their substrate independence and van der Waals nature allows for ready stacking of nanomaterials at the device (interdigitated channels) or chip (monolithic 3D...
Size dependence of random telegraph noise (RTN) in ultra-narrow silicon nanowire transistors with width far less than 10nm is experimentally measured and statistically analyzed for the first time. Single-trap RTN amplitude shows nearly exponential distributions, which reaches 170mV at 1.8% quantile for the narrowest transistor. The origins of long tail distributions and strong size dependence are...
We demonstrate junctionless tri-gate MOSFETs utilizing a single layer 7 nm thick In0.80Ga0.20As (ND ∼ 1×1019 cm−3) as both channel and contacts. Devices with source and drain metal separation of 32 nm and Lg of 25 nm exhibit SS = 76 mV/dec., both the highest reported gm = 1.6 mS/μΑ and Ion = 160 μA/μm (VDD = 0.5 V, IOFF = 100 nA/μm) for a junctionless transistor. We also examine the influence of the...
We fabricated and in-depth characterized advanced planar and nanowire CMOS devices, strained by the substrate (sSOI or SiGe channel) and by the process (CESL, SiGe source/drain). We have built a novel access resistance (RACC) extraction procedure, which enables us to clearly evidence the strong impact of back-bias and strain on Racc (−21% for 4 V Vb and −53% for −1GPa stress on pMOS FDSOI). This is...
Perpendicular Spin-Transfer Torque (STT) MRAM is a promising technology in terms of read/write speed, low power consumption and non-volatility, but there has not been a demonstration of high density manufacturability at small geometries. In this paper we present an unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS-embedded 40 Mb array. Key features are full array...
Highly reliable data compression technique. Flash Reliability Boost Huffman coding (FRBH) is proposed for TLC NAND Flash memory. By decreasing the write data size and optimizing the memory cell Vth distribution at the same time, FRBH decreases data-retention errors by 92% and increases data-retention time by over 2900 times.
7nm CMOS FinFET technology featuring EUV lithography, 4th gen. dual Fin and 2nd gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology [1]. EUV lithography, fully applied to MOL contacts and minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity and smaller CD variation. AVT of 6T HD SRAM cell are...
State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS®) has been applied for the first time in fabricating high performance wafer level system-in-package (WLSiP) containing the 2nd-generation high bandwidth memory (HBM2). An ultra-large Si interposer up to 1200 mm2 made by a two-mask stitching process is used to form the basis of the 2nd-generation CoWoS® (CoWoS®-2) to...
Embedded memories play an important role to enable applications for mobile, IoT, security and high performance computing. In this paper, we presented the SRAM and non-volatile memories for different applications.
In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported...
We present the SRAM bitcell offering from 22FDXTM (a 22nm FDSOI technology) with competitive 1.46mV-µm FinFET-like transistor mismatch coefficient (AVt) built with low cost planar architecture. Extremely low minimum operating voltages (Vmin) are reported for both the high-density (HD) 0.110μm2 and high-current (HC) 0.124μm2 bitcells without any assist, showing 95% limited yield (LY) Vmin values of...
As IoT moves beyond a catchphrase and starts to provide meaningful solutions in multiple fields, three of its critical pillars are now well understood: • Transducers are needed as means of interacting with the environment and machines, and in converting stimuli to data and vice versa. These sensors and actuators form the basis of contextual awareness. • Given that many end-node IoT devices are size...
We investigate a novel Ti Chemical Vapor Deposition (CVD Ti) technique for source/drain and trench contact silicidation. This work is a first demonstration of a highly selective, superconformal Ti process that exhibits a low p-type CVD Ti/SiGe:B contact resistivity (pc) down to 2.1×10−9 Ω.cm2 (a 40% reduction vs. PVD Ti), matching the lowest published values [1-5]. A competitive n-type CVD Ti/Si:P...
Super-steep switching is successfully demonstrated using positive feedback (PF) in fabricated diode-type 3-D NAND flash memory strings. Thanks to the PF, the subthreshold swing (SS) measured in a cell of a string during read operation is less than 1 mV/dec at turn-on voltage (Von) regardless of the polarity and the amount of the charge stored in the cell. This string has memory characteristics similar...
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