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A fully integrated digitally controlled buck VR, featuring hysteretic and PFM control for maximum light load efficiency, with 3D-TSV based on-die solenoid inductor with backside planar magnetic core in 14nm tri-gate CMOS demonstrates 111 nH/mm2 inductance density & 80% conversion efficiency.
We report high performance extremely-thin-body (ETB) Ge-on-Insulator (GOI) pMOSFETs fabricated by a new Ge condensation process with minimized temperature cycles and slow cooling-down rate. This new condensation process effectively suppresses strain relaxation during Ge condensation and creates high compressive strain. By combining the highly-strained GOI substrates with a digital etching process,...
Counterfeit ICs pose a threat to designing secure and reliable electronic systems. To better detect and prevent counterfeit ICs from entering the supply chain, an eflash based powerless non-volatile sensor using floating-gate (FG) technology is demonstrated in a 0.35μm standard logic process. By exposing the FG to the environment, the proposed sensor can record any physical tamper attempt affecting...
We demonstrate scaled high-Ge-content (HGC) strained SiGe pMOS FinFETs with very high short channel (SC) performance using a Replacement High-K/Metal Gate (RMG) flow, for the first time. A novel RMG gate stack process was introduced to create Ge-free interface-layer (IL) with excellent reliability and sub-threshold swing (SS) as low as 62mV/dec, the best reported to date for Si-cap-free SiGe FinFETs...
SiGe FinFET has been explored for its benefit of high current drivability provided by channel strain [1-5]. We have demonstrated SiGe CMOS FinFET at 10nm technology ground rules including epitaxial defectivity control, DC performance and reliability benefit [6-8]. One concern of SiGe FinFET is channel strain relaxation by fin cut process [9] inducing local layout effect (LLE), which is crucial for...
New methods were studied to reduce response time and threshold voltage drift of the FET-type hydrogen sensor. The advantages of the Pt-Ti-O gate over other sensor gate materials were demonstrated. Extending Langmuir's dissociative adsorption theory to non-equilibrium states enabled us to reduce the response time, and the negative gate bias operation with P-FET-type sensor reduced the drift. Thus,...
In this paper we present the engineering of a non-volatile 1S1R memory based on a Phase-Change Memory cell (PCM), consisting in a GeN/Ge2Sb2Te5 layer, stacked with a GeSe-based Ovonic Threshold Switching selector device (OTS). We optimize and analyze separately the two devices, and we propose for the first time an innovative reading strategy of the cross point device, enabled by the improved sub-threshold...
For the first time, the ion-vacancy-based bipolar RRAM has been demonstrated on HKMG stack of FEOL logic 14nm FinFET. A unit cell with two identical FinFETs, one serves as a control transistor and the other one is the storage with resistance switching. It is performed by the edge tunneling and with bipolar switching. More importantly, the sneak path issue in an AND-type array based on this FinFET...
In this work, we demonstrate a new concept for realizing high threshold voltage (Vth) E-mode GaN power devices with high maximum drain current (ID, max). A gate stack ferroelectric blocking film with charge trap layer, achieved a large positive shift of Vth. The E-mode GaN MIS-HEMTs with high Vth of 6 V shows ID, max 720 mA/mm. The breakdown voltage is above 1100 V.
We report the first monolithic integration of InGaAs channel transistors with lasers on a Si substrate, achieving a milestone in the direction of enabling low power and high speed opto-electronic integrated circuits (OEICs). The III-V layers for realizing transistors and lasers were grown epitaxially on the Si substrate using MBE. InGaAs n-FETs with Ion/Ioff ratio of more than 106 and very low off-state...
This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible at 500°C, (ii) TiN native oxide removal prior to poly deposition leads to an improvement in gate stack reliability below 525°C and (iii) state-of-the-art...
Everybody getting excited with the 5G, mixing cats and dogs together. But the reality is, there is physical limitations and no magic, we should cool down. Whereas a lot would get to be possible and that should not be under estimated, and we should know what would be possible and what would not. Industry experts should be able to figure out better images before it actually comes, so as not to make...
In this paper, we present a design-technology tradeoff analysis to implement a fully connected neural network using non-volatile OxRRAM cells. The requirement of a high number of distinct levels in synaptic weight has been established as a primary bottleneck for using a single NVM as a synaptic unit. We propose a mixed-radix encoding system for a multi-device synaptic unit achieving high classification...
For beyond 7 nm node BEOL, line resistance (R) is assessed among four metallization schemes: Ru; Co; Cu with TaN/Ru barrier, and Cu with through-cobalt self-forming barrier (tCoSFB) [1]. Line-R vs. linewidth of Cu fine wires with TaN/Ru barrier crosses over with barrier-less Ru and Co wires for beyond-7 nm node dimensions, whereas Cu with tCoSFB remains competitive, with the lowest line R for 7 nm...
10nm 2nd generation BEOL technology is described with an optimized illumination system and multi-patterning lithography. While the optimized illumination system offered a possibility to pattern reduced metal pitches in the preferred orientation, difficulties of T-T and T-S patterning still remained. It was overcome by increasing the number of available multi-patterning colors from 2 to 4. First-ever...
The FINFET has become widely used for nodes below 16nm. Its introduction in the manufacturing world has extended scalability of transistor dimensions. Beyond 5nm it is uncertain if the benefits of a FINFET structure will be maintained or lost. Alternative MOSFET structures may emerge to secure scaling. Nanosheet or nanowire have the potential to suppress short channel effect but these devices have...
This paper presents a smart contact lens (SCL) sensor system for successive evaluation of tear evaporation. The proposed SCL system integrated with 3D technology is composed of tunable sensitivity sensor-readout circuitry, a tear sensor, and an antenna, and is embedded into a biocompatible hydrogel-based contact lens by a commercial manufacturing process. Moreover, the on-lens system can be addressed...
We report on novel integrated Se-based Ovonic Threshold Switching selector devices, with sizes down to 50nm, which can be operated reliably at high drive current densities, exceeding 20MA/cm2, and have high half-bias nonlinearity exceeding well 103. We show functional devices after a thermal budget of 350°C. Their electrical properties are tunable by careful control of the GexSe1−x films composition,...
In this paper, we clarify a filamentary “refresh” mechanism of a resistive random access memory (ReRAM) cell. Based on this mechanism, we propose an intentional refresh introduction that enables a reduction in the standard deviation (σ) of current values. The activation energy (EA) associated with oxygen vacancies (Vos) in ReRAM was investigated using low-frequency-noise spectroscopy, revealing continuous...
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