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Embedded SRAM based memory sub-systems are an integral part of SoCs and have a large area footprint in modern SoCs today. Huge memory requirements are typically met by using an array of SRAM instances and optimal selection of these memory instances becomes imperative for SoC designers. We propose a framework based on the following approach: pre-sort a list of most suitable SRAM instances; create a...
In this paper, we introduce low-power and real-time intelligent SoCs aimed at smart machines. To implement intelligent functions under low-power consumption, machine learning methods are tightly integrated with the traditional algorithms. At first, an object recognition processor (ORP) accelerating scale-invariant feature transform (SIFT) is presented with a visual attention based on convolutional...
Cyber-physical systems are engineered systems that require tight conjoining of and coordination between the computational (discrete) and the physical (continuous). Cyber-physical systems are rapidly penetrating every aspect of our lives, with potential impact on sectors critical to national security and competitiveness, including aerospace, automotive, chemical production, civil infrastructure, energy,...
Miniaturized neural sensing microsystem has become increasingly important for brain function investigation. This paper presented a low voltage area-power-efficient 11-bit hybrid analog-to-digital convertor (ADC) with self-calibration for neural sensing application. To reduce the total amount of capacitance, the proposed hybrid ADC is composed of 3 bit coarse-tune and 8 bit fine-tune with delay-lined...
Over the years, autonomous systems have entered almost all the facets of human life. Gradually, higher levels of autonomy are being incorporated into cyber-physical systems (CPS) and Internet-of-things (IoT) devices. However, safety and security has always been a lurking fear behind adoption of autonomous systems such as self-driving vehicles. To address these issues, we develop a framework for quantifying...
This paper presents a 4.8 V tolerant circuit for reliably switching a startup load between a main power supply and a battery power supply. The circuit automatically switches the main power supply over to the battery in case the main line has been interrupted. The circuit includes a pair of back-to-back switch transistors for isolating the load from each power supply, a bias circuit for controlling...
Throughput, area and power optimized designs for the advanced encryption standard algorithm are proposed in this paper. The presented designs are suitable for the encrypt-only AES-128 algorithm. Both designs integrate pipelining and iterative architectures in one design. This is achieved through applying the concept of partial loop unrolling where iterations and multistage pipelining are used to optimize...
Pipelined and Delta-Sigma (ΔΣ) ADCs are increasingly becoming popular in mixed-signal system-on-chip (SoCs). This tutorial combines theoretical as well as practical perspectives on ADC design with special focus on two types of ADCs, viz., CT-ΔΣ ADC and pipelined ADC. The goal is to provide a complete picture to the audience, starting from system level architecture to their transistor-level design...
The past decade has seen a great deal of attention and effort focused on circuits, architectures and methodologies for energy-efficient and low power computing across a broad range of applications from ultra-low power devices to high-end servers. As designers continue to seek and evaluate low power technologies to enable the next generation of computing, the traditionally unheralded problem of voltage...
Monitoring and tracking of IP traffic flows are essential for network services (i.e. packet forwarding). Packet header lookup is the main part of flow identification by determining the predefined matching action for each incoming flow. In this paper, an improved header lookup and flow rule update solution is investigated. A detailed study of several well-known lookup algorithms reveals that searching...
A novel high-speed single-ended D flip-flop based on a SR(set/reset)-type latch is presented in this paper. The SR-type latch is adapted to implement a dynamic stage for high-speed operation and modified to add a scan mux without setup time degradation on a data path. The proposed flip-flop enables to achieve the high-speed operation having the comparable hold time characteristics to a conventional...
Gate-all-around (GAA) nanowire transistor is promising for continuing scaling down the feature size of transistors beyond sub-10nm because it provides the gate with better controllability over the channel by wrapping around. In this paper, the device model for 10nm gate length conventional GAA (C-GAA) and junctionless GAA (JL-GAA) are extracted based on the TCAD simulation. The layout design of GAA...
Memory systems like Static Random Access Memories (SRAM) and Non Volatile Memories (NVM) thrive on area and power efficient designs. This paper presents a novel and a power proficient design of a Dual Functionality Read-Write (DFR-W) driver for SRAM sub-system. This design is integrated with a memory sub-system with an operating frequency of 1GHz in CMOS 65nm technology. It is then compared with a...
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