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We utilize eye-diagram measurements of timing jitter to investigate the impact of PBTI in devices subject to DC as well as ring oscillator (RO) and pseudo-random binary sequence (PRBS) stress waveforms. We observe that RO measurements miss the relevant random timing jitter increases which are well captured using PRBS measurements. We also observe that DC, RO, and PRBS stresses all introduce similar...
We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with effective drive currents of Ieff (N/P) = 621/453 µA/µm at Ioff = 10 nA/µm at VDD = 0.8 V. The BOTS process results...
This paper presents the superior electron and hole mobility on a single orientation Ge substrate for compact and cost-effective CMOS applications. The different scattering mechanisms of electron and hole mobility are discussed for understanding carrier transport physics. On the basis of this understanding, the highest electron mobility of 437 cm2/Vs and hole mobility of 213 cm2/Vs at Ns=1e13 cm−2...
FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (Ion) variability (0.37 %µm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability...
For the first time, the breakdown path induced by BTI stress can be traced from the RTN measurement. It was demonstrated on advanced high-k metal gate CMOS devices. RTN traps in the dielectric layers can be labeled as a pointer to trace the breakdown path. It was found that breakdown path tends to grow from the interface of HK/IL or IL/Si which is the most defective region. Two types of breakdown...
An ultimate CMOS structure composed of high mobility wire channel InGaAs-OI nMOSFETs and SGOI pMOSFETs has been successfully fabricated by means of sequential 3D integration. Well behaved CMOS inverters and first demonstration of InGaAs/SiGe (Ge) dual channel CMOS ring oscillators are reported. The 21-stage CMOS ring oscillator operation was achieved at Vdd as low as 0.37 V with the help of adaptive...
Advancement in 3D integration by die and wafer level stacking has enabled a wide variety of applications. There is an increasing demand for higher capacity and functionality in Field Programmable Gate Arrays (FPGAs) to improve performance, overall power consumption and form factor. FPGA capacity can be dramatically increased by stacking multiple smaller FPGA die on a passive interposer. The required...
InGaAs FinFETs fabricated by an unique Si fin replacement process have been demonstrated on 300mm Si substrates. The devices are integrated by process modules developed for a Si-IIIV hybrid 300mm R&D pilot line, compatible for future CMOS high-volume manufacturing. First devices with a SS of 190 mV/dec and extrinsic gm of 558 µS/µm are achieved for an EOT of 1.9nm, Lg of 50nm and fin width of...
We propose and demonstrate the operation of single structure III–V CMOS transistors by using metal S/D ultrathin body (UTB) InAs/GaSb-on-insulator (-OI) channels on Si wafers. It is found that the CMOS operation of the InAs/GaSb-OI channel is realized by using ultrathin InAs layers, because of the quantum confinement of the InAs channel and the tight gate control. The quantum well (QW) InAs/GaSb-OI...
STT-MRAM is a logic-friendly nonvolatile memory that can realize a combination of high speed, low energy, and high endurance. Embedded STT-MRAM is positioned attractively not only for emerging low standby-power connectivity systems such as wearables, IOT (Internet-of-Things), and secure elements, but also for high-performance mobile SOC as an embedded nonvolatile working memory. With recent breakthroughs...
We characterized the behavior of transient bit-line current (IBL) during reading after giving a pre-bias (Vpre) to two different cells in 3-D stacked NAND flash memory having poly-Si body. Depending on the dominance of charge trapping in blocking dielectric or the interface between the tunneling oxide and the poly-Si body, opposite behavior was observed. To identify the cause, we systematically analyzed...
An ultra-thinning down to 4-µm using 300-mm wafer proven by 40-nm Node 2Gb DRAM has been developed for the first time. Three different types of thinning process including coarse grinding, fine grinding, and stress relief were optimized and an atomic level vacancy less than 10-nm in depth at backside of wafer was formed successively. Thickness uniformity even after thinning down to 4-µm was approximately...
Interconnect-related problems in the advanced technology node are identified and possible solutions are proposed. A PVD process of a double-layer Ta/TaN barrier is to be replaced with a CVD process of a single-layer barrier. Cu filling process can be changed from PVD seed deposition and electroplating to dynamic PVD reflow of Cu. Manganese and its oxide are shown as a possible choice of new barrier...
Dynamic variability of 28nm FD-SOI high density SRAMs has been directly measured and carefully modeled using a new technique based on the Supply Read Retention Voltage (SRRV) metric. It is proven that, for this technology, N&PBTI induced variability has only a small impact on the SRAM read stability after 10 years working at operating conditions.
Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control...
A cost competitive 20nm technology node is described that enabled industry-first 20nm cellular modem chip with 2× peak data rates vs 28nm, and 2× carrier aggregation. Process and design enhancements for layout context optimization, and continuous process improvements resulted in 18% boost in circuit performance while simultaneously achieving >30% power reduction. 3 mask local interconnect and 64nm...
The Internet of Things (IoT) is a rapidly emerging application space, poised to become the largest electronics market for the semiconductor industry. IoT devices are focused on sensing and actuating of our physical environment and have a nearly unlimited breadth of uses. In this paper, we explore the IoT application space and then identify two common challenges that exist across this space: ultra-low...
CMOS readout circuit is stacked on MEMS accelerometer using face-to-face (F2F) direct metal bonding. F2F bonding provides smaller form factor, latency, and power consumption. The CMOS chip acts as an active cap that encapsulates and provides interconnect routing to the MEMS chip. Metal bonding (Al-Au) was achieved at 300°C/10min/50N. The bond quality meets the requirements during shear and helium...
The RC delay and power restrictions imposed by the interconnect system can contribute to poor circuit performance in an increasingly severe manner as dimensions shrink. Resistances are increasing faster than the scale factor of the technology and capacitance improvements are constrained by mechanical requirements of the assembled stack. Collectively, these cause a bottleneck in both local and global...
The first monolithic process flow integrating silicon photonics on operational bulk CMOS has been developed. Features include deep-trench isolation, polysilicon waveguides, grating couplers, filters, modulators, and detectors. Fully functional on-chip CMOS enables Tx/Rx operation while minimizing interconnect parasitics. With the addition of an external 1280nm source, a fully functional optical link...
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