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Comprehensive studies on random telegraph signal (RTS) noise have been done to understand carrier trapping processes, with a main focus on the large variations of time constants. It is observed that time constant distributions, as well as thermal activation energy distributions, weakly depend on the substrate doping concentrations or surface orientations. For individual traps, time constants are quite...
Enhanced current drivability of BEOL-process-compatible dual-oxide complementary BEOL-FETs on LSI-interconnects (Fig. 1) with just two additional masks to the state-of-the-art BEOL process is demonstrated, aiming at high-Vbd pre-driver operation. We have developed processes so that IGZO-based NFETs have lower ARon as compared to currently available Si power devices (Fig. 6). We also developed new...
By realizing a high-quality epitaxial La2O3/ GaAs(111)A interface, we demonstrate GaAs CMOS devices and integrated circuits including nMOSFETs, pMOSFETs, CMOS inverters, NAND and NOR logic gates and five-stage ring oscillators for the first time. As an exercise of III–V CMOS circuits on a common substrate with a common gate dielectric, it provides a route to realize ultimate high-mobility CMOS on...
We present a comprehensive study of Si0.55Ge0.45-cladded p-channel FinFETs, including a comparison with planar SiGe quantum-well devices. The SiGe-cladded FinFETs exhibit ∼2× higher hole mobility, ∼2× better ION/IOFF, and improved DIBL compared to Si control devices. Superior NBTI reliability over equivalent Si FinFETs is demonstrated for cladding thicknesses down to 3 nm. The dependencies of drive...
A “shrink process” for reducing the size of a magnetic tunnel junction (MTJ) and mitigating the MTJ processing damage by using a sequence of oxidation and covering silicon dioxide (SiO2) film after MTJ etching is proposed. Using the novel process, MR (magneto-resistance) ratio was improved more than 10% and junction size was able to be reduced to 20-nm diameter in a MTJ with processing size of 35-nm...
Poly-Si thin-film transistor (TFT) is the key building element for high-density 3D NAND Flash memory. Random grain boundary (GB) location and interface traps (Dit) density have been shown as the major root cause of variability [1]. However, with CNL pinned at midgap our previous model cannot adequately address experimental results - especially the cause of very low Vt TFT devices. In this work we...
We realized an ultimately advanced imaging system that comprises a hemi-spherically curved, back-illuminated CMOS image sensor (BIS) and integrated lens which doubles the sensitivity at the edge of the image circle and increases the sensitivity at the center of the image circle by a factor of 1.4 with one-fifth lower dark current (Jd) than that of a planar BIS. Because the lens field curvature aberration...
This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using...
We live in an interconnected world. Computing power once reserved for server rooms now resides in our pockets. Tablets now outsell PCs. As marked as these changes have been, we are now entering a new era of vastly greater connectivity, where people interact with the world around them in entirely new ways. The Internet of Things is in its infancy, so predictions of precisely what it will become are...
On behalf of the organizing committee, we would like to cordially welcome you to the 34th Symposium on VLSI Technology to be held from June 9–12, 2014, at the Hilton Hawaiian Village in Honolulu, Hawaii. Since its founding in 1982, the Symposium, jointly sponsored by the IEEE Electron Devices Society and the Japan Society of Applied Physics, has long been recognized as one of the premiere international...
We perform a comparative analysis of metal-Si and metal-insulator-Si (MIS) contacts and quantify the impact of the contact/via resistances on logic performance. Our results show that silicide contacts account for 32% degradation in the ON current of an nFinFET (ION) compared to ideal contact. MIS contacts which lead to lowering of Schottky barrier height provide 12% performance gain at iso-energy...
A sidewall electrode technology was successfully developed for the first time in this study, improving the understanding of the working mechanism in an ultra small, functional HfO2-based resistive random access memory (RRAM) device (< 1 × 3 nm2). This technology exhibits potential for application in atomic-scale memories. The 1 × 3 nm2 RRAM device exhibited an excellent performance, featuring a...
Novel technology enablers for high-performance three-dimensional (3D) system integration are demonstrated in this paper: (a) A thick silicon interposer with 65 µm diameter and 370 µm tall low-loss polymer-embedded vias on a 150 µm pitch is fabricated and characterized demonstrating a 78% reduction in insertion loss compared to similar-sized conventional TSVs at 50 GHz; (b) Two dice with embedded microfluidic...
We discovered that by changing the dielectric capping layer above the phase change memory element we can change the SET speed and data retention of the memory. This allows us, for the first time, to integrate memories of different functions on the same chip with simple processes. By using a low temperature silicon nitride capping material we can get fast SET speed down to 20ns. With a high temperature...
Despite improved device performance over traditional Poly-SiON technology, high-K metal gate flow introduces additional device variations not previously seen in Poly-SiON process, especially impacting large dimensional (WxL) devices for matching critical applications. For the first time, we report a comprehensive analysis of device variations introduced from metal gate process, GDIM and GGIM, and...
Conventional phase change memory (PCM) stores information in amorphous/crystalline states that can be read out as HRS/LRS. In this work we report a radically different mode of storage that can concurrently and independently work with the conventional storage mode. By stressing the memory cell with current we can shift the threshold for RESET switching, and the resulting R-I curve can be used to store...
An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CETINV-normalized GM,SAT,INT of 6.7 nm.mS/µm, the Si0.3Ge0.7 / sGe pFinFETs presented in this work improve the performance by ∲90% as compared to...
An advanced Replacement Metal Gate (RMG) module was developed for 14nm node FinFETs and beyond. STI oxide extra recess increases on-current without any dedicated Source and Drain (SD) optimization. Tungsten (W) selective etch recesses work function metal (WFM), which reduces gate-contact capacitance, and improves AC performance and yields by increasing gate-contact space. Combination of work function...
Threshold voltages (Vt) in high κ nFETs are observed to shift under prolonged positive gate bias stressing. This bias induced Vt shift (ΔVt) is referred as PBTI and is an important reliability issue. In this paper, we extend a previously proposed PBTI model to include de-trapping kinetics. The proposed model is verified by comparing calculated results with PBTI data measured over a wide range of stress...
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