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For 20nm SoC products, we propose an SRAM macro with low dynamic and leakage power. This is achieved by adopting an interleave word-line and hierarchical bit-line scheme, in which minimum portions of circuits are activated when SRAM is accessed. Measured data confirms that the proposed 128kb SRAM realizes 600 mV operation, 2.1 µW/MHz active power and 82 % leakage power reduction.
For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline. Meanwhile, presented technology also provides advantage in SRAM cell size by 20% scaling down. It can furthermore offer potential of beyond 10nm Si-based CMOS computing circuit technology.
A 14KB 8T-bitcell SRAM array is demonstrated in 22nm tri-gate CMOS with fine-grain dual-VCC assist techniques. VMIN limiting 8T-bitcell nodes are boosted selectively during read and write to improve overall chip-VMIN. Measurements show 130–270mV lower VMIN with 27–46% lower power at 0.4-1.6GHz for varying amounts of boosting, array activity and voltage regulator efficiency.
We demonstrated record 0.37V minimum operation voltage (Vmin) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to the small variability of SOTB (AVT∼1.3 mVµm) and adaptive back biasing (ABB), Vmin was lowered down to ∼0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.
A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 µm2 DRAM cell capable of meeting >100µs retention at 95°C. Results will be reported for a test-vehicle with best-reported array density at 17.5Mb/mm2 based on a 128Mb macro. The process...
We demonstrate for the first time, Si1−xGex channel trigate PFETs on insulator with aggressively scaled fin width WFIN, gate length LG, and high-K/metal-gate stack (inversion oxide thickness TINV = 1.5 nm) using an implant-free raised source/drain (RSD) process. We report excellent electrostatic control down to LG = 18 nm for WFIN ≤ 18 nm. Using an optimized RSD process, we achieved high-performance...
This work proposes an 8T cell with dual data-aware write-assist (D2AW) and negative read-WL (NRWL) schemes to increase the figure of merit (FOM): [cell stability (CS)*cycle frequency (f)]/[cell area (A)*minimum VDD (VDDmin)]. The column-based D2AW provides, for the first time, the solution to the trade-off between the row/column half-select (HS)-CS margins and the write margin (WM) thanks to the dual...
Abstract A discrete-time ΔΣ ADC that utilizes an 8b SAR quantizer with a 4b feedback DAC is presented. The 4 MSBs of the quantizer are fed-back for Δ operation while a digital filter post-processes the full 8b and improves the resolution. The ΔΣ modulator has a single stage 2nd order feed-forward topology with Fs=240MHz and OSR=8. The ADC achieves 66dB SNDR, 15MHz bandwidth, and consumes 12.7mW power...
A VCO-based delta-sigma modulator (ΔΣM) is proposed for bio-potential signal acquisition. The VCO quantizer is placed in a loop with 1-bit feedback to improve modulator linearity. Furthermore, frequency calibration employing gated VCO technique is proposed to improve the operation range. Fabricated in a 0.18µm CMOS, this chip consumes 379nW and occupies an active area of 0.06mm2. Over a 2kHz signal...
A machine-learning (ML) assisted cardiac sensor SoC (CS-SoC) is designed for healthcare monitoring with mobile devices. The architecture realizes the cardiac signal acquisition with versatile feature extractions and classifications, enabling higher order analysis over traditional DSPs. Besides, the dynamic standby controller further suppresses the leakage power dissipation. Implemented in 90nm CMOS,...
An extremely low power and area efficient threshold configuring ADC (TC-ADC) is proposed. The threshold configuring comparator (TCC) performs a binary search and only 1b-DAC is required. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in...
This paper presents an ultra-low-power filter bank design for digital hearing aids. A novel time borrow & local boost (TBLB) scheme for aggressive voltage over-scaling is proposed, which does not incur cycle penalty on the rescue of timing violations, and is thus suitable for hardwired ASIC. The measured power of the test chips with the straightforward filter implementation can outperform those...
A highly adaptive multi-sensor SoC comprising four on-chip sensors and a smart wireless acquisition system is first realized in standard CMOS process. To intelligently process different types (C/R/I/V) of sensor signals, a linear (R2 = 0.999) and reconfigurable sensor readout is proposed. A two-input energy harvesting interface with conversion efficiency of 73 % is also integrated for long-term use...
A versatile signal reconstruction platform designed in a 40nm CMOS process is presented. The chip supports high-dimensional sparse signal reconstruction for compressed sensing and sparse representation. A 4G entries/s (8Gbps) high-throughput sensing matrix generation engine is proposed. It r educes o ver 7 5% external bandwidth and 77% processing cycles. The chip achieves 401GFlops/W power efficiency...
This paper describes a 5GS/s 6bit flash ADC fabricated in a 32nm CMOS SOI. The randomness of process mismatch is exploited to compensate for dynamic offset errors of comparators that occur during high speed operation. Utilizing the proposed calibration, comparators are designed with near-minimum size transistors and built-in reference levels. The ADC achieves an SNDR of 30.9dB at Nyquist and consumes...
We present a quadrature VCO based on mutual parametric pumping between two LC resonators. The design occupies 0.11mm2 in 65nm CMOS, consumes 16.8mW, and achieves a phase noise of −116.7dBc/Hz at 1MHz offset from a 6.57GHz carrier, while providing CMOS quadrature outputs. The measured phase error is less than 0.3° across the entire tuning range. Relative to state-of-the-art quadrature VCOs, it compares...
A 0.3V parametric resonance based sub-GHz injection-locked frequency multiplier is developed in 90nm CMOS. This is the first reported variation-tolerant frequency multiplier with 0.3V supply voltage. It achieves 720µW power consumption and −110dBc@600kHz phase noise with the lowest supply voltage in state-of-the-art frequency synthesizers.
This paper presents a 2.5b/stage pipelined time-to-digital converter (TDC). For pipelined operation, a novel time-register is proposed which is capable of storing and adding time information with a clock signal. Together with a time-amplifier, a 9-bit synchronous pipelined TDC is implemented which consists of three 2.5b stages and a 3b flash TDC. A prototype chip fabricated in 65nm CMOS achieves 1...
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