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A 6-port, 2-lane packet-switched input-buffered wormhole router forms the key building block of a 2×2 2D mesh network-on-chip (NoC). The router operates across a wide frequency (voltage) range of 1GHz (0.85V) to 67MHz (340mV), dissipating 28.5mW to 675µW and achieves 3.3X improvement in energy-efficiency at an optimum supply voltage (VOPT) of 400mV. The resilient router incorporates an end-to-end...
Double-patterning lithography is required at 20 nm node for planar CMOS. At the 16 / 14 nm node, in order to deliver attractive amount of Performance-Power-Area enhancement, 3-D FinFETs are required. Close collaboration at design ecosystem among fabrication foundry, EDA vendors, IP vendors, packaging vendors, and design houses is crucial for successful migration to FinFET circuits. This paper describes...
The ever increasing stress engineering raises a major concern of strong layout-dependent effects (LDE) in the advanced technology nodes. We report on the dependency of SiGe S/D and STI induced stress on fin length, position of the gate along the fin and fin to fin distances. The efficiency of epitaxial S/D SiGe stressors is reduced when the fin length is decreased and strongly degraded for fins with...
This paper presents the implementation details and silicon results of a 2.6GHz dual-core ARM Cortex A9 manufactured in a 28nm Ultra-Thin Body and BOX FD-SOI technology. The implementation is based on a fully synthesizable standard design flow, and the design exploits the great flexibility provided by FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.6V to...
Key elements of FDSOI (Fully Depleted Silicon on Insulator) technology as applied to SRAMs are described. Thick- and thin-Bottom Oxide (BOX) variants are discussed.
A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency...
A pipelined ADC employs charge-steering op amps to relax the trade-offs among speed, noise, and power consumption. Applying full-rate nonlinearity and gain error calibration, a prototype realized in 65-nm CMOS technology achieves an SNDR of 52.2 dB at an input frequency of 399.2MHz and an FoM of 53 fJ/conversion-step.
Resistive RAM (RRAM) faces two major design challenges: 1) cell area versus write current requirements; 2) cell current (ICELL) versus read disturbance. An RRAM using logic-process-based vertical parasitic-BJT (VPBJT) switches and correspondent cell array (VPBJT-CA) can achieve 4.5+x smaller macro area. To overcome temperature-dependent fluctuation in the base-emitter voltage difference (VBE) of BJT,...
A wide-field fluorescence lifetime imager capable of up to 100 frames per second (fps) is presented. The imager consists of a 64-by-64 array of low-noise single photon avalanche diodes (SPADs) in a standard 0.13-µm CMOS process, 4096 time-to-digital converters, and an application specific data path to enable continuous image acquisition at a total output data rate of 42 Gbps. These features combine...
A direct-conversion transceiver including base-band amplifiers and filters employs a 60-GHz quadrature VCO and a feedforward divider with no buffers to achieve a low power consumption. Designed in 40-nm LP CMOS, the radio presents a noise figure of 4.8 to 8.2 dB in the receive mode and an output power of +10 dBm in the transmit mode while drawing 56 mW and 124 mW, respectively.
A 4-element 60-GHz phased-array receiver employs transformer-based hybrid-mode mixing featuring high linearity and high gain. Closed-loop beam-forming calibration is achieved by sequentially performing gain equalization, I/Q calibration, and successive-approximation phase tuning. Implemented in 65nm CMOS, each element measures NF of 6.5dB, gain of 20dB and IP1dB of −12.5dBm. With the proposed beam-forming...
A 2D/3D image sensor with reconfigurable pixel array and column-level background suppression scheme is presented for high resolution outdoor imaging. The proposed pixel array employs pixel binning and superresolution techniques for adaptable resolution. The sensor achieved a 5.9µm pixel and was able to capture full resolution outdoor depth images under daylight over 100klx.
A non-volatile CBRAM macro embedded with a body sensor node processing platform operates at low voltages down to 600mV for write and 300mV for read, enabling ultra low energy operation, compatibility with energy constrained digital systems, and no need for charge pumps.
A novel ultra-low-power MCU is presented, which is optimized for both lowest stand-by and active power consumption. By modifying technology, adopting critical blocks in circuit design, and tailoring the system architecture the MCU achieves an overall stand-by current consumption of 350nA. This number includes the real time clock functionality, the 32kHz crystal oscillator, and the supply voltage supervision...
A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. At 28 GHz the RMS jitter is 199fs (1MHz to 1GHz), phase noise is −110dBc/Hz at 10MHz offset. The 140×160µm2 32nm SOI CMOS PLL locks from...
A new power-efficient, reconfigurable, 6th-order continuous-time bandpass delta-sigma modulator architecture is presented. A new duty-cycle-controlled DAC halves the number of DACs in the modulator, and also enables the center frequency to be reconfigurable. A prototype 800MS/s modulator achieves 69dB SNDR with a 25MHz bandwidth at a 200MHz IF. The center frequency can be varied from 180MHz to 220MHz...
This work demonstrates a 3D vertical-gate (3DVG) NAND Flash with circuit-level techniques to overcome degradations in speed, yield, and reliability resulting from cross-layer process variations. The key enables include: (1) layer-aware program-verify-and-read (LA-PV&R), (2) layer-aware-bitline-precharge (LA-BP), and (3) a wave-propagation (WP) fail-bit detection (FBD) scheme. A fabricated 2-layer...
This paper proposes a 0.18um CMOS vision sensor that combines event-driven asynchronous readout of temporal contrast with synchronous frame-based active pixel sensor readout of intensity. The sensor is suitable for mobile applications because it allows low latency at low data rate and therefore, low system-level power consumption. The image frames can be used for scene analysis and the temporal contrast...
A fast and accurate Approximate Nearest Neighbor (ANN) searching processor is proposed to resolve the main bottleneck of the real-time object recognition process, the ANN searching. A new scheme, Spatio-Temporal Locality searching (STL-searching), is proposed to reduce the external memory bandwidth by at least 78x compared to Locality Sensitive Hash (LSH) scheme. However, the STL-searching suffers...
We have developed an image sensor with thin organic photoconductive film (OPF) laminated on CMOS circuits. Owing to high capacity of a charge storage node, the saturation level is 12 dB higher than those of conventional image sensors. Because of the very thinness of the laminated film, i.e. 0.5 µm, the device is crosstalk-free and an incident light angle of over 30 degrees is realized.
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