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This work demonstrates a 3D vertical-gate (3DVG) NAND Flash with circuit-level techniques to overcome degradations in speed, yield, and reliability resulting from cross-layer process variations. The key enables include: (1) layer-aware program-verify-and-read (LA-PV&R), (2) layer-aware-bitline-precharge (LA-BP), and (3) a wave-propagation (WP) fail-bit detection (FBD) scheme. A fabricated 2-layer...
A ternary content-addressable memory (TCAM)-based hardware called nonvolatile “multi-functional CAM (MF-CAM)” is proposed for an ultra-low-energy “full-text search” system in recent data centers. The proposed nonvolatile MF-CAM-based full-text search engine can perform parallel comparison while eliminating leakage energy by hierarchical power gating. By the massively parallel comparison with the hierarchical...
A “scalable 3D-FPGA” using TSV interconnects is proposed. This FPGA was designed on the basis of homogeneous 3D-stacking to extend the logic scale in proportion to the number of stacked layers. To improve Z-axis transmission performance, a wafer-to-wafer stacking process for lowering the capacitance of TSV was developed. An “embedded TSV“ design for the shorter on-chip wirings was also devised. Moreover,...
We optimize and investigate extensively the sub-μA bipolar operation of scaled Al2O3- and HfO2-based RRAM cells using carefully thinned dielectrics and Hf scavenging layer. Although isotropic scaling favors the sub-μA operation, switching variability remains intrinsically large due to low number of involved O-vacancy switching species. The low filament temperature also accounts for slow forming/set...
Time of flight (ToF) sensor with pixel size of 7×7um and VGA resolution is developed using a backside illumination (BSI) structure. Quantum efficiency (QE) of near infrared (NIR) light is improved dramatically by applying thick epitaxial layer, reflection metal and anti-reflection layer. The depth error ranges are 2cm and 10cm at 90% and 10% reflection condition at the distance of 7m, respectively.
A 6-port, 2-lane packet-switched input-buffered wormhole router forms the key building block of a 2×2 2D mesh network-on-chip (NoC). The router operates across a wide frequency (voltage) range of 1GHz (0.85V) to 67MHz (340mV), dissipating 28.5mW to 675µW and achieves 3.3X improvement in energy-efficiency at an optimum supply voltage (VOPT) of 400mV. The resilient router incorporates an end-to-end...
Resistive RAM (RRAM) faces two major design challenges: 1) cell area versus write current requirements; 2) cell current (ICELL) versus read disturbance. An RRAM using logic-process-based vertical parasitic-BJT (VPBJT) switches and correspondent cell array (VPBJT-CA) can achieve 4.5+x smaller macro area. To overcome temperature-dependent fluctuation in the base-emitter voltage difference (VBE) of BJT,...
It is found that traps inside conduction and valence bands of Ge is the dominating factor of effective mobility reduction for Ge MOSFETs in high Ns region and that surface roughness scattering can quantitatively explain the Hall mobility, which is free from the trapping effects. It is also found that atomic deuterium PDA sufficiently reduces the trap density inside conduction band of Ge, resulting...
We have developed an image sensor with thin organic photoconductive film (OPF) laminated on CMOS circuits. Owing to high capacity of a charge storage node, the saturation level is 12 dB higher than those of conventional image sensors. Because of the very thinness of the laminated film, i.e. 0.5 µm, the device is crosstalk-free and an incident light angle of over 30 degrees is realized.
We report the first demonstration of strained In0.53Ga0.47As-on-insulator (-OI) MOSFETs on Si substrates using the direct wafer bonding (DWB) technique. 1.7 % highly-strained In0.53Ga0.47As-OI structures were successfully fabricated on Si by DWB. Strained In0.53Ga0.47As-OI MOSFETs with Ni-InGaAs metal S/D have successfully operated, for the first time. MOSFETs with 1.7 % tensile strain exhibits 1...
We have fabricated high-quality, high-uniformity GeSn-On-Insulator in a low-temperature process compatible with Si CMOS and BEOL to enable monolithic 3D integration. Excellent interface roughness and electrical passivation are demonstrated.
The exascale computing is required in the Era of Big Data. In order to achieve this demand, new technology innovation must be required and packaging scaling including 3D-IC with TSV (Through Silicon Vias) is one of most promising technology. To increase the total bandwidth, the fine pitch die to die interconnection is necessary. Micro-bumping, thermally enhanced underfill and advanced interposer technologies...
To reduce TSV coupling noise, a new guard-ring technique is proposed and implemented experimentally. We design the n+/n− well guard-ring butted to the TSV dielectric surrounding the TSV and utilize the inversion layer induced by a positive interface charge as a shield layer. The interface trap density responsible for the interface charge between the TSV dielectric and Si substrate was extracted. Proposed...
Heterogeneous integration of integrated circuits offers an opportunity to create new functionality with tradeoffs between cost, performance, and alternative monolithic integration complexity. We present a study of heterogeneous integration using a large, field programmable gate array (FPGA) research and development vehicle to assess the capabilities of 3D silicon interposer technology. This study...
We report the first demonstration of gate-all-around (GAA) GeSn nanowire (NW) pFETs. The uniaxially compressive strained GeSn NW with a width of 50 nm and a height of 35 nm was fabricated using a CMOS compatible top-down approach. The GeSn GAA NW pFETs with the shortest reported channel length LCH down to 100 nm were realized, and the devices achieve a record high peak intrinsic transconductance G...
We calculate band offsets for FinFETs with strained SiGe- and strained InGaAs-channels on strain relaxed buffers (SRB) and provide specific guidelines to optimize quantum wells, metal gate work functions, and mobilities for group-IV and group-III/V devices.
We report InAs/In0.53Ga0.47As channel MOSFETs using source-drain regrown contact and surface digital etching. A device with 40 nm-Lg shows 2.45 mS/µm extrinsic peak transconductance gm at VDS = 0.5 V and 214 Ω-µm Ron. A long-channel device (Lg = 510 nm) exhibits 1.06 mS/µm gm at VDS = 0.5 V and 93 mV/dec at VDS = 0.05 V. At all gate lengths, the devices exhibit the highest extrinsic gm among published...
We demonstrate on-chip pattern recognition in a neural network circuit using a non-volatile memory for the first time. The synapse chip of the neural network consists of a stack of CMOS circuits and three-terminal ferroelectric memristors (3T-FeMEMs). By using the analog and non-volatile conductance change of the 3T-FeMEM as a synaptic weight, the matrix patterns are learned. Even when an incomplete...
Field Effect Transistors on SOI offer inherent capacitance and process advantages. The flow of heat generated at the drain junction may be impeded by dielectric isolation but an assessment must also account for conduction of heat through the gate stack and through the device contacts, and its impact on device characteristics should be captured by the scalable model to enable accurate circuit design...
The nature of threshold switching (TS) in AsTeGeSiN-based selector devices is comprehensively investigated. The scaling of the AC response is limited up to 5 ns due to a finite intrinsic delay time. An analytical model allows the accurate prediction of the TS nature, which can be merged to a numerical circuit simulation for providing essential guideline of the required selectivity performance.
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