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A class of negative differential resistance circuits is developed for realization with standard NMOS/CMOS processes. The circuits are optimized in regard to the negative slope and the power dissipation. There are both pure NMOS and CMOS and mixed NMOS/CMOS circuits which have been simulated, designed and realized. The circuits are well suited for VLSI memories, multiple-valued logic and adaptive systems...
For high-speed GaAs integrated circuits ICs) of LSI complexity to be realized, a technology with low-power dissipation with maintaining circuit speed must be used. Previous GaAs research at Honeywell has focused on the conventional depletion-mode GaAs MESFET, which is capable of only MSI circuits [1-2]. Depletion-mode gate arrays using buffered FET logic (BFL) have demonstrated 1.3 mW at 740 ps per...
This paper presents an interactive CAD system for switched capacitor filters. This system handles the entire design process from specifications up to mask generation, all automatically. The original features of this system are: 1) powerful synthesis and simulation programs, 2) complete interactive and graphical editors for the electrical circuit and layout, 3) unique circuit description and electrical...
Using a 4 ??m silicon-gate CMOS technology a mixed analog-digital multi-function chip has been developed, which enables the digital access to and from the subscriber line as part of an ISDN (Integrated Services Dig ital Network) interface module. The transmit path of the chip incorporates a I4th-order digital FIR filter, a D/A converter and a power opamp which drives the subscriber line. In the receive...
A 1.3 GHz dual stage i.c. for logarithmic successive detection (s.d.) amplifiers is described. A complete amplifier using three i.c.' s achieves a signal compression accuracy of ?? 1dB over an input dynamic range of 65dB at a frequency of 450MHz. This device is aimed at electronic support measures (e.s.m.) systems and is also applicable to high performance signal regenerators such as those used in...
This paper describes a CMOS 7 bit flash analogue to digital converter capable of operation at sample rates in excess of 22 MSPS with an analogue bandwidth to ???? 1sb of 5MHz. The device has been realised on a 2.5??m double layer metal CMOS process. Monotonicity is guaranteed by the decoding scheme and the accuracy is defined by the inherent matching of the device threshold voltages in the comparator...
The analog part of a high-resolution A/D converter has been integrated in a compatible 3-5 ??m CMOS-JFET technology. The circuit, which forms a pulse density modulator (PDM), can be operated at sample rates up to 12 MHz and reaches a SNR of 84 dB over a baseband of 20 kHz. This corresponds to approximately 14 bit A/D resolution.
A number of ECL integrated circuit designs, based on high reliability uncommitted logic arrays, are being developed at BTRL to enable the upgrading of the UK trunk transmission network from 140Mbit/s to 565Mbit/s. The performance of two of the designs has been reported in this paper, and it has been shown that the components offer ample speed margin for a fully integrated system.
There will be in the near future, a strong demand for ultra high speed, medium resolution analogue to digital (A/D) converters to be used in various field of applications such as oscilloscopy, telecommunication systems and especially radar signal processing. 8 bit, 100 MHz converters are already available in silicon technology; but the need is rather in the gigabit range which seems, at least today,...
This paper aims to present a new switch level simulator for MOS VLSI design. The simplicity of its algorithms and its rapidity are felt to be attractive for designers. As an introduction, we will situate the switch level as a good alternative to the boolean gate level of description. In the second section we will briefly discuss two existing simulators, FLOGMOS and MOSSIM 2. Finally in third section,...
Since the first microprocessor, built in 1971, micro-processors have evolved at a dramatic pace in terms of technology, processing power, dissipation, and functionality. This paper makes a brief overview of the history, presents major areas of importance in design and summarisizes some approaches that are currently being considered for the future. The 4 bit 4004 from INTEL CORP. was the first micro-programmable...
This paper describes the architecture and the design of a high performance single chip Radix-2 FFT Butterfly. The architecture is optimized to a very efficient bit-serial data processing and to a pipeline-parallel hardware structures. The design is based on a standard cell approach including LSSD test capabilities. The circuit has been fabricated at CNET (centre of Meylan Grenoble France) as part...
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