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Using an advanced bipolar trench technology, a high density I2L type memory cell has been fabricated in a 1K static RAM test vehicle. By maximizing the utility of the trench, the 1K RAM contains a cell with high density and large signal for extension to 256K.
A first monolithic programmable multichannel stimulator for cochlear prosthesis has been successfully implemented in 2 ??m Si-gate CMOS technology. The stimulator is to be implanted in the mastoid bone. The system provides separate transcutaneous power and data links and can stimulate 15 cochlear electrodes simultaneously with different stimulus currents.
This paper describes a new smart temperature sensor with on-chip signal processing. The output signal consists of a temperature-dependent frequency and a reference frequency that are time multiplexed and can be read out by a mirocomputer. This sensor, which has been designed for biomedical applications, has a temperature range from 30??C to 46??C, an accuracy of ??0.1??C, a resolution of 0.01??C and...
Novel complementary CAM/RAM circuits feature very short access time (3.4 nsec), high density (6 and 8 minimum size device/cell) and radiation hardness (1 ?? 106 rad (Si)) in a hierarchical organization of 4k bit memory modules. The design utilizes innovative static memory cells and operating scheme, optimized fault-tolerant modular architecture and 1.25-2??m advanced CMOS VLSI process.
A 256k (32k ?? 8b) 5V-only EEPROM with high-density structure cell has been developed. The EEPROM, offering typically 150ns address access time, 80mW active, and 1??W standby power dissipation, was successfully fabricated by a single-polysilicon and single metal CMOS process with a 1.2 ??m photo lithography.
This paper deals with the design of a low cost ECL bipolar compatible I.C performing the function of four balanced full-duplex transceivers particularly suitable for interconnections long up to several tens of meters in digital systems. One of the most interesting applications of this circuit is in the field of wideband digital switching (up to 100 Mbit/sec) where the amount of two-way internal connections...
A CMOS single chip edge detector capable of processing two dimensional blocks of 3 ?? 3 points of data to rates of 15MHz is presented. The chip has been implemented on a 2 micron bulk CMOS process, using the Megacell design methodology, the layout completed using an interactive editor with on-line design and electrical rule checking.
A new high performance 16 bit NMOS microprocessor is presented which is dedicated to time critical multitask applications. A hardware implemented task scheduler allows the handling of up to 8 concurrent tasks with a medium restart latency time of 5.25 ??s. The memory address space is 1 Moyte and the I/O space 128 bytes. High regularity in chip layout is achieved using bitslice technique in the data...
The breakthrough of fully digital, computer controlled telephone switching technology and its consequent evolution towards fully digital, end to end communication in an integrated services digital network which unites a wide variety of voice and non voice services, has only come about with recent advances in microelectronics. After a brief introduction on system structure, this paper will summarize...
The step to full Nyquist operation of an 8-bit flash ADC with a sampling rate of up to 120 MHz, as reported in this paper, was achieved using new solutions for the improvement of linearity and for the compensation of signal delays. Together with a proper comparator circuit and a speed power optimized encoding structure, this led to excellent dynamic performance up to 60 MHz full scale analog signals...
A bipolar masterslice cell array with 9K gate complexity has been developed. The 128 mm2 chip features ECL100K/10K compatibility, 20 W typical power dissipation, and 320 pins (256 logic, 64 supply). The on-chip gate delay is 150 ps.
A monolithic microwave frequency divider IC with an operating range of 1.4 - 5.3 GHz was developed and fabricated in a standard bipolar technology. The circuit operates on the principle of "regenerative frequency division". Compared to the more popular divider concepts based on a master-slave D-flip-flop, a much higher input frequency can be divided. A further advantage is the low power...
AN EXPERIMENTAL 8K BIT, HIGH PERFORMANCE, STATIC BIPOLAR RAM HAS BEEN DESIGNED AND FABRICATED IN TRENCH ISOLATION TECHNOLOGY. A NOMINAL ACCESS TIME OF 6 NS WAS DEMONSTRATED FOR SATURATED AND SCHOTTKY BARRIER DIODE (SBD) CLAMPED VERSIONS OF THE MULTI-EMITTER COMPLEMENTARY TRANSISTOR SWITCH (CTS) CELL; AND A PREDICTED WORD LINE RECOVERY PROBLEM FOR THE SATURATED VERSION WAS VERIFIED BY HARDWARE TESTING...
Low temperature MOS devices (77K) present significant gain in speed and density for a low technological cost. We report results concerning a three bits adder fabricated with an adapted cryogenic N-MOS process, using Argon-implanted polysilicon loads; the maximum measured frequency was 405 MHz for a 28 mW power consumption, with 2.4?? design rules.
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