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This paper presents a procedure for electrical parameter extraction of high voltage SOI MOS transistors. Several types of NMOS and PMOS fully depleted SOI devices were measured and modelled in a voltage ranging up to 30V. The standard Berkeley BSIMSOI3 model with ICCAP software was applied as a basis for modelling work. In order to increase the maximum operation voltage of the MOSFETs, a number of...
Si surface properties and electrical characteristics in n- and p-MOSFETs with 2-6 degree tilted off-axis (110) channel were investigated for the first time. The transconductance of p-MOSFET with off-axis channel was significantly degraded than that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved than that of normal channel. The changes were larger than those observed...
EKV3 is a circuit-design-oriented compact MOSFET model for analog/RF IC design. The paper presents parameter extraction guidelines and modelling using EKV3 for TOSHIBA's 90 nm RF-CMOS technology covering DC, CV and RF (S-parameter) and temperature scalability. RF verification was done by the use of multi-finger MOSFETs with many variations of gate length, width of unit fingers and number of fingers...
We describe the transient floating-body mechanism which occurs in fully depleted SOI transistors and leads to a memory effect. A physics-based model for the potential variation with time is proposed and validated by numerical simulations. This model reproduces and clarifies the operation of the novel capacitor-less MSDRAM, the properties of which are discussed.
This paper discusses methods for query execution and optimization in object-oriented grid databases. The queries for distributed databases have become even more complex. This cause a difficulty for query execution and optimization process, which requires advanced algorithms and techniques to reduce processing and communication cost. This paper gives the outline of distributed data processing, which...
This paper describes high temperature image quantitative analysis systems. The specificity of measurements based on images presenting heat-emitting objects is considered. Particular attention is paid to computerised system for surface properties determination. A brief description of the system is given. The measurement process is presented. Problems connected with processing images of hot objects...
The paper discusses efficiency issues of piezoelectric transformers in a step-down DC/DC converter application. With the development of piezoelectric technology, these compact non-magnetic devices are becoming an interesting alternative to traditional transformers in a wide range of electronic equipment. Despite high declared efficiency (above 90%), heat effects resulting from energy loss are still...
The main aim of the presented researches was to design and implement algorithm for eyelids localization that would be applied in iris recognition system. The authors' method searches for eyelids based on two criteria - presence of edges in the grayscale image of eye and intensity value in the sclera region. The algorithm was implemented in C++ language and was integrated in the iris finder - authors'...
This paper discusses an idea for power-saving mode in application specific processors in the domain of digital signal processing. This idea is based on a multiple (in practice double) accumulator model, which is used in order to obtain high accuracy in a series of floating-point additions. The goal is to introduce a possibility of reducing the power consumption without reducing the functionality....
This paper presents the basics of fast orthonormal parametrical transform called as "Constant Rotation Angle In Matrix Orthonormal (orthogonal) Transform" (CRAIMOT), briefly described in [1]. This transform can be treated as a parametrical transform or a class of transforms. Some examples of shapes of basis functions (BFs) are presented. The algorithm for generation of CRAIMOT BF is based...
A method for reliable measurement of interconnect delays is presented in the paper. The mode of test vectors generation never induces crosstalks. That is why the delay measurement is reliable. Also, minimization of ground bounce noises and reduction of power consumption during the test is an additional advantage. The presented method allows also localizing and identifying static faults of both stuck-at...
This paper presents a novel step-ramp signal (SRS) for testing analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). A regulated clock signal (RCS) comes from regulating the frequency, duty cycle and amplitude of the system clock pulse which also serves as a trig pulse of a reference counter. The RCS is integrated by an Integrator to transform into the SRS which can accurately...
The paper deals with a modification of CBCM (charge-based capacitance measurements) for nonlinear capacitance characterization. The method is characterized by high resolution although it is based on equipment found in any average laboratory. CBCM was originally developed for linear interconnect measurements. The proposed modification uses two DC swept sources to measure the whole nonlinear Q-v characteristic...
This paper presents an original testing board dedicated for SI ASIC chips. The board is based on a programmable logic device, which generates the required signals for the tested chip. The parameters of the signals are set with a simple interface. The project was written in a VHDL and implemented in Xilinx CPLD. The board was used to test a new structure of a SI integrator, and the results are also...
This paper presents method of deriving optimal excitation signal maximizing probability of successful fault diagnosis. The approach uses evolutionary algorithm and wavelet analysis. The diagnosis procedure is conducted by means of specialized aperiodic excitation. Results are compared with fault diagnosis using unit step excitation. The method belongs to simulation before test (SBT) class of fault...
This paper describes a new method of random access memory faults description using VHDL language. The fault injection technique, which uses behavioral synthesis VHDL descriptions, is proposed. The injection can be easily automated for memory test algorithms verification using only VHDL language and standard simulation software. No other applications and simulation tools are needed.
The arrival of CMOS integrated systems into nanoscale dimensions is presenting many challenges to designers and manufacturers concerning yield and reliability of integrated circuits. Traditional techniques to cope with these subjects are not as effective as they were before and many solutions are considered to allow CMOS evolution to continue according to Moore's law. Among the proposed solutions...
A designing of digital circuits is based on hardware description languages (HDLs). The dominating standard of HDLs is the VHDL, which basing on a digital circuit structure, a net-list, and an event-driven algorithm. In the publication is presented a description of the digital circuit built in an object-oriented programming. The base assumptions of a description are a digital circuit diagram and an...
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