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This paper presents the characterization of substrate noise coupling and the isolation capability of ohmic substrate contacts in a HV CMOS technology. Layout variations of contact sizes, distances, and several p+ guard structures are subject of this research. Metal shielded DUT fixtures have been developed to improve the reliability and accuracy of the measurements. All test cases are fabricated with...
In this paper the current distribution within woven electroconductive textile sheets was investigated using a computer program written for the purpose of the simulations. An iterative method of solving very large resistor networks used to model textile sheets is discussed. The factors taken into account are the conductivity of the fibres, the contact resistance between the fibres, the contact angle...
The results of thermal characterization of actively cooled high-power laser bars are presented. The experimental data obtained by thermal imaging is compared with modelling of temperature distributions in the packaged device. The temperature differences between the central part and the edges of the array are determined. Moreover, we present the microscopic scale temperature profiles in-junction plane...
This paper presents the basis of dynamic thermography, with its application to thermal parameters evaluation. The method is based on windowed FFT analysis, with special attention paid for the phasegrams interpretation. A thermal modeling of the investigated object based on lumped RC network has been made to estimate the sensitivity and accuracy of the method. Heat transfer coefficient, thermal conductivity...
The paper presents new supervisors dedicated to predictive methods of dynamic power management, i.e. DCT (dynamic clock throttling), DFS (dynamic frequency scaling), and DVS (dynamic voltage scaling). The presented supervisors make decisions on the basis of current chip temperature; future, current and previous power dissipations. They consist in cooperation with operating system and they are dedicated...
This paper presents the electrothermal simulation of integrated thin film resistors. Both the thermal and electrical problem is tackled by a semi-analytical method, without the need of generating an equivalent distributed network. As the electrical conductivity is temperature dependent, self-heating of the resistor will alterate the current distribution, leading to a non-uniform power dissipation...
The main goal of this paper is to present an extension of a numerical solver dedicated to thermal simulation of electronic structures. This solver implements the finite difference method and employs the RC equivalent network approach. The hereby-proposed extension renders possible thermal simulation taking into account non-linear cases when material thermal properties and heat transfer coefficient...
The paper describes real, successive steps of the design of fully integrated QVCO for 2.4 GHz. First version of the design, correct in simulation, does not fulfil the requirements when it was measured. The detailed reasons of changes introduced in the design are presented. Comparison of measured tuning characteristic with simulated one proves the validity of design steps.
This paper introduces a fully differential opamp with constant large-and small-signal behavior rail-to-rail input stage. A compensation strategy is presented to extend the bandwidth. The linearity issue of the compensation is discussed. A test chip is implemented in a standard 120 nm CMOS process, with the measured signal variation of about 4.43% as well as a GBW of 135 MHz. Experimental results verify...
In this paper the design of a CMOS cascoded operational amplifier is described. Due to technology scaling the design of a former developed operational amplifier has now overcome its stability problems. A stable three stage operational amplifier is presented. A layout has been created automatically by using the ALADIN tool. With help of the extracted layout the performance data of the amplifier is...
In this paper, the fixed size processor array architecture, which is destined for realization of LLT-decomposition of symmetrical positively definite matrices based on Cholesky algorithm, is proposed. In order to implementation of this architecture in modern FPGA devices, the arithmetic unit (AU) operating in the rational fraction arithmetic is designed. This AU is adapted to realization in the Xilinx...
This paper presents the design and implementation of a combined, interval and conventional floating point multiplier, which operates with IEEE 754 numbers. The proposed unit consists of a floating point multiplier - which computes several results of the same operation (rounded differently) - and of two floating point comparator circuits. This architecture implements an algorithm that is suitable for...
This paper discusses design of an field programmable gate array (FPGA) based hardware accelerator for a standard cell placement tool. A software program was used to determine the bottlenecks in the simulated annealing (SA) algorithm with greedy perturbations and dynamic cooling schedule. A solution implementing computing platform with specialized hardware configurations inside an FPGA was investigated...
This article covers the topic of designing the operational amplifiers, it describes the design of a compact, low power amplifier utilizing 0.35 μm CMOS technology. The main motivation behind this work was the existing need at the Technical University of Lodz for compact device that could be easily employed in larger designs. This article describes best topology for each stage in terms of meeting the...
In this paper we present Matlab analysis as well as CMOS implementation of an analog current mode Kohonen neural network (KNN). The presented KNN has been realized using several building blocks proposed earlier by the authors, such as: binary tree winner take all circuit, Euclidean distance calculation circuit, adaptive weights change mechanism. The example network contains four neurons, each of them...
In this paper we present a multiple-valued gate using pseudo floating-gate. One of the key advantages is the possibility to operate this gate in continuous mode. The avoidance of recharging the floating-gate (recharge-signal) is shown to be quite liberating and to possess new and powerful qualities. Simulation results are provided.
This paper presents a kick-back reduced comparator based on a sense-amplifier type comparator. The kickback charge and resulting voltage peak is reduced by 6times, which corresponds to a power reduction in the input driver and the resistance ladder of the same magnitude. A 4-6-bit 3-GS/s low-power flash ADC using the proposed comparator has been implemented in a 90 nm CMOS process. The significantly...
Static power consumption due to excessive leakage currents is a major problem in CMOS digital ICs with gate lengths of 90 nm and below. In this paper the physics and modelling of these currents is discussed, with special emphasis on variability and its effect on the statistical spread of the static power consumption and total power consumption.
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