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This paper introduces a new method combining low frequency actuation signal as test stimuli and envelope detection on the RF (radiofrequency) output signal to provide a low cost mean for offline as well as for online testing of RF MEMS switches. The study includes the modelling of RF MEMS switches as well as some ideas how to test online and diagnose their functionality. The proposed approach uses...
This paper proposes a new current sensor design for the arduous task of testing embedded analog and mixed-signal circuits. This proposed, wide-band, minimally-intrusive IDD sensor operates up to 230MHz, which is 2.3X faster than previously proposed designs, and occupies 78.3% less area than another competing design, while achieving an inherent tolerance to process and temperature variations without...
High defect rate in emerging nano-devices mandates new computational models that can tolerate defects thereby rendering reliability of operation and reasonable manufacturing yield. In a bottom-up system design approach using nano-crossbar applications are typically mapped into a crossbar using either PLA or lookup table (LUT) implementation of a logic circuits. LUT-based implementation has some definite...
In this paper, an efficient technique for designing RAMs for on chip correction of double errors integrated on H-tree memory architecture is discussed. The reliability of the proposed design is improved by 8X while the Mean Time To Failure is improved 3X while comparing to traditional Hamming codes for a 256 Mbits memory chip. The area is sacrificed for these reliability improvements, significant...
This paper presents a technique to derive and implement error detectors to protect an application from data errors. The error detectors are derived automatically using compiler-based static analysis from the backward program slice of critical variables in the program. Critical variables are defined as those that are highly sensitive to errors, and deriving error detectors for these variables provides...
In this paper, a new methodology is proposed to improve digital circuit signal integrity, in the presence of power-supply voltage (Vdd) and temperature (T) variations. The underlying principle of the proposed methodology is to introduce on-line additional tolerance, by dynamically controlling the instant of occurrence of the clock edge trigger driving specific memory cells. On-line, dynamic delay...
This paper presents a methodology for analyzing the behavior of nanometer technologies regarding "multiple event transients" (MET) caused by nuclear reaction induced by atmospheric neutrons. For the first time, currents collected by several sensitive areas of an ASIC cell resulting from a nuclear reaction are addressed by simulation. Libraries of several thousand types of currents are obtained...
Silicon technology evolution over the last four decades has yielded an exponential increase in integration densities with steady improvements of performance and power consumption at each technology generation. This steady progress has created a sense of entitlement for the riches that future process generations would bring. Today, however, classical process scaling seems to be dead and living up to...
Infant Mortality problems have been around for a long time (maybe that is why sometimes we have a shorter warranty period for many electronic products). Anyway, the explanation of infant mortality is that these are left over (or latent) defects. Defects that do not necessarily expose themselves and they can skip by all the manufacturing tests, including system test. However, with electrical and thermal...
Summary form only given. Circuit failure prediction predicts the occurrence of a circuit failure before errors actually appear in system data and states. This is in contrast to classical error detection where a failure is detected after errors appear in system data and states. Circuit failure prediction is performed during system operation by analyzing the data collected by sensors inserted at various...
In the accelerated soft-error rate (SER) testing of embedded SRAMs usually only a few samples of a given device are tested, often only for a checkerboard data pattern and at the nominal supply voltage. In this paper it is demonstrated, using a 90-nm test vehicle, that there is a significant sample-to-sample variation in SER and a strong dependency on the data state of the bit-cell. The well-known...
Radiation-induced soft errors are getting worse in digital systems manufactured in advanced technologies. Stringent data integrity and availability requirements of enterprise computing and networking applications demand special attention to soft errors in sequential elements and combinational logic. This tutorial will discuss the impact of technology scaling on soft error rates, circuit-level modeling...
The following topics are dealt with: reliability issue in nanometer technology; network-on-chip reliability and fault tolerance; secure systems; large scale dependability; SoC and asynchronous circuits; radiation effects; signal integrity and error compensation; on-line testing; parallel multi-core chips; processor-based testing; self-checking and self-testing.
Summary form only given. We mainly address here the "alter ego" of quality, which is reliability, and is becoming a growing concern for designers using the latest technologies. After the DFM nodes in 90 nm and 65 nm, we are entering the DFR area, or design for reliability straddling from 65 nm to 45 nm and beyond. Because of the randomness character of reliability - failures can happen anytime...
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