In the accelerated soft-error rate (SER) testing of embedded SRAMs usually only a few samples of a given device are tested, often only for a checkerboard data pattern and at the nominal supply voltage. In this paper it is demonstrated, using a 90-nm test vehicle, that there is a significant sample-to-sample variation in SER and a strong dependency on the data state of the bit-cell. The well-known voltage dependency causes an additional spread in the observed SER. Samples processed in different corners show a small but significant variation, which is not directly linked to speed. Simulations show that this variation is not caused by a spread in the critical charge, but is due to a difference in charge collection efficiency. The observed spread in SER tends to increase with technology scaling and should be taken into account when an SRAM technology is characterized.