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This paper presents a robust and novel technique for the circuit simulation of ESD (electrostatic discharge) snapback characteristic. A new linearization scheme for the avalanche current model in ESD evaluation shows a good convergence behavior during ESD stress simulation. This technique is compatible with the traditional circuit simulator based on the modified nodal analysis (MNA) like SPICE. We...
Intrinsic parameter fluctuations, arising from the granular nature of charge and matter, are predicted to be a critical roadblock to the future CMOS 6-T SRAM scaling. A hierarchal simulation methodology, which can fully collate intrinsic parameter fluctuation information into compact model sets, is employed to investigate the impact of random dopant fluctuation on SRAM static noise margin, and the...
We have developed MOSFETs noise models for the 1/f, thermal and induced-gate noise based on self-consistent surface-potential description. Consideration of non-uniform mobility and carrier distributions arising from the surface potential distribution along the channel is indispensable for accurate noise modeling for RF applications. The developed noise models are implemented in the complete surface-potential...
Channel segments approach is used to investigate NQS (non-quasi-static) effect on MOSFET's behavior. For the first time, NQS effect on terminal currents is examined in addition to channel charge. It is demonstrated that conventional analysis and modeling approach for NQS effect, which only takes into consideration the NQS effect on channel charge, is not sufficient. Both channel charge variation and...
A bias-dependent QM correction for surface potential calculation is derived for DG MOSFETs. The QM-corrected surface potential agrees with the 2D simulation results well. This indicates that both Vth shift in the subthreshold and strong inversion regions and gate capacitance degradation in the strong inversion region due to QM are predicted simultaneously. The model can predict the complicated QM...
Design of complex systems relies on accurate compact models for circuit simulation. In nanoscale MOS devices a model for the potential barrier limiting the channel current is required. In this paper a closed-form analytical model for 2D effects on the barrier is derived. This model is very close to device physics, without including numerical fitting parameters
Compared with conventional SiON MOSFETs, p+-poly-Si gated MOSFETs with atomic-layer-deposited Si-nitride/SiO2 stack gate dielectrics exhibit quite different bias temperature instability (BTI) behaviors: NMOS under positive BT stress degrades significantly with the stress voltage increasing; PMOS under negative BT stress exhibits a turnaround threshold voltage shift; etc. The abnormal BTI behaviors...
In this paper, the dynamic negative bias temperature instability (DNBTI) characteristics of p-MOSFET with N-plasma SiON dielectric are studied. Under dynamic stress, the nearly consistent frequency dependent characteristics of threshold voltage shift (DeltaVth) and interface trap density (DeltaNit) were observed. The results show that the degradation and recovery of DNBTI are still dominated by the...
Since the end of the last millenium, the microelectronics industry is facing new issues as far as CMOS devices scaling is concerned. Linear scaling will be possible in the future if new materials are introduced in CMOS devices structure or if new devices architectures are implemented. The demand for low voltage, low power and high performance are the great challenges for the engineering of sub 50nm...
Among emerging issues on nanoscale MOSFETs, two aspects are discussed. One is a new type of parasitic capacitance in MOS capacitors, and the other is analysis of channel transport in terms of a newly developed reflection-transmission formalism. The non-zero thickness of charge layer in the MOS gate electrode causes a new type of parasitic capacitance, which is comparable to and is equally serious...
This paper is submitted with an investigation concerning the effects of the Si thickness-induced variation of the electrical characteristics in the FDSOI with block oxide. We noticed that the traditional sidewall spacer process is used and processed to produce the block oxide enclosing the Si-body in our proposed structure, the undesirable ultra-short-channel effects can be significantly diminished...
We are trying to submit with this paper a new concept concerning the partial silicon-on-insulator (SOI) process, aiming to fabricate the self-aligned pseudo-SOI device structures - (a) the silicon on partial insulator with block oxide FET (bSPIFET), and (b) the partially insulating oxide (PiOX) under source/drain (S/D) (PUSD) partially insulated field-effect transistor (PUSD PiFET) (Yeo et al., 2004)...
The 2005 International Technology Roadmap for Semiconductors predicts a printed minimum MOS-transistor channel length of 9 nm for the year 2020, which results in a physical gate length of only 6 nm. The resolution of optical lithography still dramatically increases, but known and proved solutions for structure sizes significantly below 50 nm do not exist until now. Above these dimensions the known...
The mechanism responsible for the short-channel electron mobility (e$mobility) abnormal degradation in n-type tall fins multiple-gate field-effect transistors (MuGFETs) has been identified. RF-CV measurement, mobility extraction, and 1/f noise measurements have been performed and point to a larger process related density of traps (N t) at the gate edges. These traps and their distribution along the...
For the first time, partially-depleted silicon-on-insulator (PDSOI) accumulation-mode dynamic threshold (AMDT) pMOS with TiSi2 /n-Si as reverse Schottky barrier (RSB) is reported. By this RSB scheme, AMDT pMOS can be operated beyond 0.7 V, which is the drawback of conventional DT pMOS with gate and body connected (GBC). Compared with normal AM pMOS, AMDT pMOS with RSB reduces threshold voltage by...
In this paper, the temperature impact on the Lorentzian noise induced by electron valence band tunneling (EVB) is analyzed for partially depleted SOI MOSFETs. In (Lukyanchikova et al., 2003) and (Lukyanchikova et al., 2004) the Lorentzian noise parameters were already studied at 300K and a model based on shot noise of the EVB tunneling current was proposed. The aim of this paper is to investigate...
The scaling down issues in the charge trapping memory are investigated in this work. In the sub-100 nm devices, the punch-through problem, as well as high program voltage and electrical field limitation are studied by device simulation and measurement. The authors found CHE program mechanism meet certain limitation in the future short channel devices. Furthermore, program induced charge distribution...
A flash memory cell with 90nm ground-rules has been embedded in a high performance (HP) CMOS logic process. A novel deep trench isolation (DTi) process module enables an isolated pwell (IPW) bias scheme, leading to flash with uniform channel program/erase (UCPE) by Fowler-Nordheim (FN) tunneling without GIDL, a key feature for low-power (LP) electronics. IPW leads to a compact cell design and a highly...
Scaling down of conventional flash memory technology faces difficult technical challenges and some physical limitations. Novel silicon-based flash cell structures were presented in this paper as possible solutions. A novel cell structure using dual doping polysilicon (PNP) as the floating gate is proposed and experimentally exhibit higher programming speed and better data retention characteristics...
NOR and NAND flash memories have scaled over 9 generations and 20 years since their 1986 product introductions. This scaling of both memory types in conjunction with MLC technology have enabled the cellular phone market and digital still camera market with high density code and removable data storage. This paper will discuss how flash technology scaling continues to enable new solutions for both the...
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