The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A novel method for on-line fault detection and location in network-on-chip (NoC) communication fabrics is introduced. This approach is able to distinguish between faults in the communication links and faults in the NoC switches. The idea is based on the use of code-disjoint routing elements, combined with parity check encoding for the inter-switch links. We analyze the effect of our method on relevant...
This paper reports a case study about the automatic layout generation and transient fault injection analysis of a phase-locked loop (PLL). A script methodology was used to generate the layout based on transistor level specifications. After layout validation, experiences were performed in the PLL in order to evaluate the sensibility against transient fault. The circuit was generated using the STMicroelectronics...
Systems on a chip (SoCs) in safety-critical applications need features such as built-in self-test, on-line self-test and error compensation of transient faults. With ever-shrinking feature size, also built-in self-repair (BISR) may become a must. While BIST and BISR are well understood and frequently implemented for embedded memory blocks, BISR for random logic is by far an unsolved problem. Logic...
Designing secure ICs requires fulfilling many design rules in order to protect access to secret data. However, these security design requirements may be in opposition to test needs and testability improvement techniques that increase both observability and controllability. Nevertheless, secure chip designers cannot neglect the testability of their chip; a high quality production testing is primordial...
This paper presents practical results on the evaluation of fault countermeasures implemented in an asynchronous DES coprocessor. The theory underlying the countermeasures was previously published in IOLTS 2005. For the first time this work reports a practical evaluation of fault countermeasures applied on asynchronous DES ASICs. Two DES crypto processors were fabricated using the 130 nm STmicroelectronics...
A significant fraction of soft errors in modern microprocessors has been reported to never lead to a system failure. Any concurrent error detection scheme that raises alarm every time a soft error is detected is not well heeded because most of these alarms are false and responding to them will affect system performance negatively. This paper improves state of the art in detecting and preventing false...
The problem of fault tolerance and fault resistance is becoming more and more important in all application fields. In this context, asynchronous designs provide inherent properties that make them attractive to design robust systems. Moreover, hardening techniques can be applied at the design time to improve their fault resistance with low area, speed and power costs. This work presents the latest...
This work discusses the use of two fault-tolerant techniques, duplication with self-checking and triple modular redundancy, for one-hot encoding FSM in SRAM-based techniques. The FSM encoding styles have a significant influence on the dependability of the machine in presence of bit-flips, known as single event upsets (SEUs). Although the one-hot encoding style presents the best trade-off in terms...
Single-event latchup is one of the most threatening single event effects as the induced current may destroy the affected device. Existing latchup mitigation schemes may induce a very high area cost or may require modifying the fabrication process. In this paper we present a new single-event latchup mitigation approach implemented at design level that protects devices from destruction and preserve...
Reconfigurable compute fabrics (RCFs) are cellular architectures in which an array of computing elements and a configurable interconnection fabric are combined with a general-purpose processor. RCFs can play an important role in safety- or mission-critical applications, provided that a clear understanding of their dependability is available. In this paper, we report an evaluation of the effects induced...
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults
In this paper, a novel on-line error detection technique for wireless RF transmitters is proposed. Spectral features of the real time streaming data are monitored at the baseband input of the system to trigger the on-line tests whenever specific conditions on these spectral features are met. Embedded spectral sensors at specific RF nodes that generate DC output values are used to monitor the spectral...
Recently, various attacks have been proposed against many crypto systems, exploiting deliberate error injection during the computation process. In this paper, we add a residue-based error detection scheme to an RSA architecture to protect against such attacks. We then evaluate the error coverage and the expected area and latency overheads
Comparison between synchronous and asynchronous models leads to a protocol-based fault model for asynchronous circuits. Protocol monitoring of the control path is separated from data comparison in the data path. A novel protocol decomposition technique is used to extract simple protocols from behaviour of a complex circuit. This technique is implemented as a software tool. An asynchronous checker...
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerbate process variations and reduce noise margins, worst-case design will eventually fail to meet an aggressive combination of objectives in performance, reliability, and power. In order to circumvent these difficulties, researchers...
Summary form only given. The quality of electrical tests during irradiation of components has also improved a lot. Test patterns have been modified and characteristics of recent DRAMs have had to be taken into account. We can also observe a trend in the results of soft error tests. In the beginning, we mostly got single-bit events and did not ask for more. The trend is now moving toward a complete...
With ongoing technology scaling, reliability is becoming increasingly important for integrated circuits (ICs) manufactured in deep-submicron CMOS technologies. The reliability issue that generally leads to the highest failure rates is that of radiation-induced soft errors. Both alpha particles, emitted by chip and package materials and cosmic neutrons are capable of inducing bit errors in ICs. These...
In this paper we demonstrate how error-correcting addition and multiplication can be performed using self-checking modules. Our technique is based on the observation that a suitably designed full adder under the presence of any single stuck-at fault produces the fault-free complement of the desired output when fed by the complement of its functional input. We initially apply conventional parity-based...
In this paper we evaluate the probability that a transient fault (TF), multiple or single, affecting a checker of a self-checking circuit, gives rise to an unnecessary error indication (no-harm alarm). A new property (no-harm alarm robustness) has been defined that, in case of a fault affecting a self-checking circuit (SCC), guarantees that we can determine whether the fault is affecting the functional...
Emerging technology is enabling the design community to consistently expand the amount of functionality that can be implemented within integrated circuits (ICs). As the number of gates placed within an FPGA increases, the complexity of the design can grow exponentially. Consequently, the ability to create reliable circuits has become an incredibly difficult task. In order to ease the complexity of...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.