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A junction barrier controlled Schottky rectifier integrated silicon carbide MOSFET (SiC JMOS) is proposed in this paper, which merged a double implanted MOSFET (DMOS) and junction barrier controlled Schottky diode (JBS) in a monolithic SiC device without any additional process and area penalty. JMOS device in this work exhibits a lower reverse conduction voltage drop than conventional SiC DMOS. There...
This paper investigates the effect of negative gate bias voltage (Vgs) on the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs. The device's ability to withstand energy dissipation during avalanche regime is a connoting figure of merit for all applications requiring load dumping and/or benefiting from snubber-less converter design. The superior material...
Passivation films on the termination area of 4H-SiC diodes were investigated to clarify the origin of a positive charge accumulation that induces instability of the breakdown voltage. A method to differentiate measured depletion layer capacitance is proposed as a way to analyze the positive charge density after applying voltage stress. Samples with different passivation films were fabricated to compare...
In this paper, a simple self-aligned process for defining short channels in 3.3-kV SiC DMOSFETs is presented and designed using a TCAD simulation. The proposed process involves channel definition by Al ion implantation at a tilted angle through the source mask and eliminates the complicated hard mask etching process. The simulation results show that implantation of 1× 1013 /cm2 and 450 keV at a 30°...
In this study, we constructed a novel measurement setup with a large current rating to measure fast Id change, and evaluated the decrease in Id due to positive AC gate bias, using commercially available SiC MOSFETs. In addition, by comparing the obtained fast 7d change results with the threshold voltage (Vth) shift measured by a conventional DC gate stress test, we verified that the conventional DC...
Pressure contact packages have demonstrated an improved reliability for silicon devices due to the elimination of the weak elements of the packaging, namely wirebonds and solder. This packaging approach has not yet been widely studied for SiC devices, however, it is of high interest for applications like HVDC or rail traction, where the wide bandgap properties of SiC devices can be fully exploited...
In this paper, we propose a novel backside design for Relaxed Field of Cathode (RFC) diode which realizes high avalanche stability and Undamped Inductive Switching (UIS) capability. In the case of the conventional RFC diode, wide recovery SOA is realized by forming p-layer on the backside of the edge termination area which reduces the carrier concentration at on-state and suppresses the carrier concentration...
A latch-up immune robust SCR with an N+ top layer and an additional Nwell region (Nwell2) is proposed in this paper. The N+ top layer and Nwell2 divide the original SCR into three new SCRs with sharing emitter, which provide the deeper ESD current (Iesd) path to improve the holding voltage (Vh) and failure current (It2). The relation between Vh and base-concentration (Nb) for LVTSCR is given to provide...
This paper proposes a 90nm bulk BiCDMOS platform for automotive applications. In this platform, two types of characteristic deep trench isolations are introduced. One has a top-to-bottom air-gap which serves as a stable isolator against high voltage. Another has a tungsten plug which not only minimizes area and resistance for substrate grounding but also slims down a noise-blocking active barrier...
In this work, we developed an effective technique to form a sharp and stable crystalline oxidation interlayer (COIL) between the reliable LPCVD (low pressure chemical vapor deposition)-SiNx gate dielectric and recess-etched GaN channel. The COIL was formed using oxygen-plasma treatment, followed by in-situ annealing prior to the LPCVD-SiNx deposition. The COIL plays the critical role of protecting...
The paper presents an integrated digital communication technique for sending gate signal and gate driver configuration data. As an application example, the developed CMOS gate driver carries the digital data through an optical isolation, in the context of wide bandgap power transistors. The receiver chip integrates all the required functions from the optical receiver to the signal processing circuit...
A new concept to realize self-protected ESD structure for 700V high side gate drive IC without additional process steps and area penalty is presented. The device was verified by simulation and confirmed by experimental results. A parasitic NPN structure integrated in high voltage level shifter LDMOS enables LDMOS to be operated within safe operating area when ESD strikes the high side driver part...
In this paper, we propose a Split-Recessed-Gate LDMOS (SRG-LDMOS) which minimizes HCl degradation with negligible increase in specific on-resistance. In SRG-LDMOS structure, the gate poly is split into two parts, the primal gate on the channel and the secondary recessed gate on the STI. This secondary recessed gate is nominally connected to source to minimize the HCl degradation although it is possible...
GaN's properties of low Coss, Crss, and lack of reverse recovery make it a more efficient power switch versus silicon. These characteristics enable higher-frequency hard-switched topologies such as totem-pole bridgeless power factor converter (PFC) that cannot be realized by silicon MOSFETs and insulated-gate bipolar transistors (IGBTs) due to their high switching losses. To take advantages of these...
This paper proposes a novel LDMOS structure with ultra-shallow trench isolation (USTI) and p-buried layer in 0.18um BCD technology platform. This platform offers 18V to 40V LDMOS devices which has best-in-class specific on-resistant (Ron, sp) with respect to similar technologies. USTI structure is implemented in LDMOS drift region to reduce specific on-resistance (Ron, sp) by shortening the current...
The Ron sp of a DMOS operated at high side (Ron_sp_HS) in the power management ICs is usually underestimated by taking the measured value at low side operation (Ron_sp_LS). The Ron_sp_HS is increased drastically when a revise voltage is applied between drift region and substrate because the drift-region is depleted and the current path is narrowed. In this paper, a novel structure with a varying-junction-depth...
Shielded-gate trench or “Shield RESURF (REduced SURface Field)” MOSFETs have been well known for its lower RDS(ON) ×Area, and lower Rds(on)×Qgd figure of merits (FoMs), and used widely in the low to medium voltage applications (25 V to 200 V). However, this improvement is achieved at the expense of higher output capacitance or output charge (Coss or Qoss), which has become an increasingly important...
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