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The development of a network centered life has increased overall data rates in core networks. Thus, data centers face the challenge to provide always more services at higher data rates while reacting quickly to complex failures and more powerful attacks thanks to efficient network forensics. Moreover, Software-Defined Networking (SDN) becomes a standard which offers agility but also requires forensic...
Space solar array simulators (SSASs) typically use linear power stages to guarantee high dynamic performance. However, commercial SAS modular products widely used in aerospace power supply system testing require multiple modules in parallel, to improve the output power level and efficiency. This paper proposes a simple thermal design for the linear power stage of an SSAS, which combines a linear power...
FPGAs are very sensitive to their operating conditions which can induce runtime errors. To prevent timing errors, FPGA manufacturers propose static timing analysis tools to ensure that the application to be implemented in the FPGA will work correctly at the expected frequency. However, that static timing analysis is corner-based and is thus valid for a set of optimal or recommended operating conditions...
Recent technological advances allowed the word to construct several wearable products that can capture and process the human body bio-signals. The PPG signal becomes one of the most contenders in heart rate monitoring due to their prominent features, flexibility, effectiveness and low costs. This paper present a novel System of PPG Heart rate calculation based on FPGA, using the Pan and Tompkins as...
The paper presents the natural extension DTC principle of three level diode clamped voltage inverter fed induction motor. This technique is based on a simple algorithm using look-up table for a three-level inverter established from a standard two-level inverter. The control algorithm is implemented using Field Programmable Gate Arrays (FPGA) with VHDL coding.
The detection of the fundamental frequency and phase angle of the positive sequence grid voltages are utmost necessary for the proper operation of controlled active power converters, which require to operate stable and robust even during the presence of diverse power quality issues. There exist various utility grid synchronization and detection methods based on Phased-Locked Loop (PLL) techniques...
In this paper we introduce a jigsaw-puzzle model to instill an entrepreneurial mindset in students. We then use our model to craft and add innovative lab assignments to “Digital Systems”, which is a core course taken by Electrical Engineering, Computer Engineering and Computer Science students worldwide. In each lab assignment, students are provided with some components or puzzle pieces as well as...
In this paper we focus on the issues of hardware implementation of genetic algorithms (GA) in hardware. In their classic implementation, the genetic algorithms search for a global minimum or maximum of a multidimensional function called the fitness function. If the problem, i.e. the fitness function, is too complex for a brute force search, we can look for a solution based on GA. In this situation...
Underwater communication with autonomous underwater vehicles (AUVs) has strong demands on the modems caused by the constantly changing signal propagation (multi-path propagation, scattering, diffraction and refraction at thermal layers, etc.) of the underwater channel. These demands typically lead to a modem designed to match specific conditions. In this paper we present an automated model-based physical...
High level synthesis tools offered by either FPGA (Field Programmable Gate Array) vendors or from the public domain are evaluated in order to generate efficient and low complexity computational intelligence modules. This paper reports specific issues and comparative synthesis results in implementing basic modules of the FSVC classifier (Fast Support Vector Classifier) and cellular automata starting...
This paper reports on the Field-Programmable Gate Array (FPGA) real-time implementation of a vector control scheme, by means of hardware-in-the-loop simulation. This approach will be applied for a PMSM used to propel an electric scooter, preceding its integration in a more complex experimental setup. The emerging need for powerful, flexible system-on-a-chip (SoC) platforms for developing complex drive...
The transition effect ring oscillator (TERO) based true random number generator (TRNG) was proposed by Varchola and Drutarovsky in 2010. There were several stochastic models for this advanced TRNG based on ring oscillator. This paper proposed an improved TERO based TRNG and implements both on Altera Cyclone series FPGA platform and on a 0.13um CMOS ASIC process. FPGA experimental results show that...
We present a click-element-based asynchronous loop structure for control path of asynchronous micro-control unit (MCU). The loop, which has one-stage control circuit instead of cascade circuits, can be triggered by only one trigger signal and stopped by a preset number. To verify the loop structure, we design an asynchronous MCU simulated in FPGA. The experimental results show that the MCU can be...
Data compression technology is the necessary technology in the age of big data. Compared with software compression techniques, hardware compression techniques can improve speed and reduce power consumption. LZMA is a lossless compression technology, and its hardware implementation has broad application prospects. This paper proposes a novel high-performance implementation of the LZMA compression algorithm...
This paper presents the FPGA implementation of neuron block units based on a sigmoid activation function for artificial neural networks (ANNs) applications. The Coordinate Rotation Digital Computer (CORDIC) algorithm has been employed for the approximation of sigmoid activation function. The proposed design was simulated using ModelSim XE II and synthesized using Altera's Quartus II with a Cyclone...
In this paper, a low-cost accelerator for the ηT pairing in characteristic three over the super-singular elliptic curves is designed. As the critical operations of ηT pairing, the cubing and sparse multiplications over GF(36m) in the Miller's algorithm are merged and their arithmetic are modified and scheduled to reduce the intermediate data related overhead. With these optimizations, the Miller's...
In this paper, a new method of generating white Gaussian noise sequence in a single clock is proposed. To obtain the high throughput, we use an optimized implementation structure of the m-sequence on FPGA, and the mapping between uniform distribution and Gaussian distribution is realized based on non-uniform partition quantization method. The Gaussian sequence is filtered by FIR filter to meet the...
In view of the contradiction between the demand of high-speed digital-to-analog converter chip and the actual chip manufacturing process and its cost, this paper introduces the principle of random equivalent sampling and realizes the realtime sampling rate 50M Equivalent sampling rate of 1.6G modules. The module includes sampling trigger module, sampling clock generation module, short time measurement...
A design and implementation method of radar time domain waveform based on FPGA is presented in this paper, in order to achieve the waveform library building, waveform selection or agility in the transmitter of cognitive radar system. First, the resident phase method and the waveform parameter design method are used to feedback the emission waveform parameters. Then, the DDS (Direct Digital Synthesizer)...
In this paper, compact memory strategies for partially parallel Quasi-cyclic LDPC (QC-LDPC) decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle, the throughput of the decoder is increased. We...
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