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Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-core architectures. This is due to the many attractive features these memory technologies posses: high density, low leakage, and non-volatility. However, the latency and energy overhead associated with the write operations...
While a number of acoustic localisation systems have been proposed over the last few decades, these have typically either relied on expensive dedicated microphone arrays and workstation-class processing, or have been developed to detect a very specific type of sound in a particular scenario. However, as people live and work indoors, they generate a wide variety of sounds as they interact and move...
Data gathered from sensor networks can easily reach the dimension of millions of data points. While there exists a great variety of sophisticated components for web-based data visualization, efficient and timely data retrieval is a non-trivial problem when dealing with large data sets. In this paper, we present a client-server architecture for a web application that allows a user to interactively...
The well-known memory wall problem has motivated wide research in the design of caches. Last-level caches, whose misses can stall the processors for hundreds of cycles, have received particular attention. Strategies to modify adaptably the cache insertion, promotion, eviction and even placement policies have been proposed, some techniques being better at reducing different kinds of misses. For example...
The financial crisis is presented around the world and has affected China economy indirectly. The objective of this article is to study the impact of the crisis on performance of listed logistics companies and finds out what field it affects. In this article, we take 64 listed transportation & ware-housing companies as research objects. Applying factor analysis and Wilcoxon rank test, we find...
With the current limitations of network technology, jumbo frames provide a mechanism that can allow greater amount of data transfer efficiently on cables. Implementation of jumbo frames is a viable option on Gigabit Ethernet. In this research undertaking, the authors implement jumbo frames on a test-bed implemented with Windows routers and performance related metrics are measured for both IPv4 and...
As the importance of non-functional requirements has increased, many researchers have become interested in software development process for non-functional requirements including the notation, modeling, and assessment of non-functional requirements. However, the characteristics of non-functional requirements are so sophisticated that there have been many topics that should be defined more clearly....
Recently, the trend of Cloud Computing has become a significant impact for IT departments and forms many innovative services by virtualization. Virtual systems have been used and identified on services of different fields nowadays. IT hardware manufacturers such as HP, IBM, Dell, etc..., put a large amount of investments on enterprise server products to support the virtualization environment. Service...
Naval Air Systems Command (NAVAIR) is responsible for cradle-to-grave development and support of Aircraft Launch and Recovery Equipment (ALRE). As this equipment and its associated development, maintenance, and support become increasingly complex, and the budgetary pressures facing the Navy become increasingly strong, there arises a need for an Integrated Support Environment (ISE) for ALRE. For the...
Modern parallel performance measurement systems collect performance information either through probes inserted in the application code or via statistical sampling. Probe-based techniques measure performance metrics directly using calls to a measurement library that execute as part of the application. In contrast, sampling-based systems interrupt program execution to sample metrics for statistical...
We apply the notion of trust to situations of document editing, to select the successive editors of the document and avoid unnecessary readings by all collaborators after each modification. Two mechanisms using trust to improve that process are proposed, and compared to the situation without trust. Simulation results suggest that trust can improve the efficiency of the collaborative work.
This paper describes an energy-aware methodology that identifies custom instructions for critical code segments, given the available data bandwidth constraint between custom logic and a base processor. Our approach enables designers to optionally constrain the number of input and output operands for custom instructions to reach the acceptable performance considering the energy dissipation of the registerfile...
Although web sites applications are not new in hospitality industry, their evaluations are not well established within hotel sector. While there are no literature has converged on a universal definition, web sites effectiveness that will be referred in this study is on their ability to meet users' preferences, mainly business travelers. Thus, this paper aimed to investigate the business travelers'...
Number of cores per multi-core processor die, as well as variation between the maximum operating frequency of individual cores, is rapidly increasing. This makes performance binning of multi-core processors a non-trivial task. In this paper, we study, for the first time, multi-core binning metrics and strategies to evaluate them efficiently. We discuss two multi-core binning metrics with high correlation...
Time-consuming cycle-accurate MPSoC simulation is often needed for debugging and verification. Its practicability is put at risk by the growing MPSoC complexity. This work presents a conservative synchronous parallel simulation approach along with a SystemC framework to accelerate tightly-coupled MPSoC simulations on multi-core hosts. Key contribution is the implementation strategy, which utilizes...
Reliable RFID identification is one of issues in RFID applications in recent. However, the RFID reader has difficulty to obtain reliable data in data capture layer. The reason is that unreliable readings such as a false positive reading and a false negative reading and missed readings can happen by reader collision problems, noise, or the mobility of tagged objects. We introduce performance metrics...
This paper examines online player performance in EverQuest II, a popular massively multiplayer online role-playing game (MMORPG) developed by Sony Online Entertainment. The study uses the game's player performance data to devise performance metrics for online players. We report three major findings. First, we show that the game's point-scaling system overestimates performances of lower level players...
With transistor miniaturization leading to an abundance of on-chip resources and uniprocessor designs providing diminishing returns, the industry has moved beyond single-core microprocessors and embraced the many-core wave. Scalable cache coherence protocol implementations are necessary to allow fast sharing of data among various cores and drive the many-core revolution forward. Snoopy coherence protocols,...
Future many-core chip multiprocessors (CMPs) and systems-on-a-chip (SoCs) will have numerous processing elements executing multiple applications concurrently. These applications and their respective threads will interfere at the on-chip network level and compete for shared resources such as cache banks, memory controllers, and specialized accelerators. Often, the communication and sharing patterns...
Existing studies on performance analysis of R&D funding have focused only on the object of measurement, and have not considered potential relations among various influential factors. In this paper, we developed performance indices to investigate further at individual company level. Empirical analysis was performed using the performance survey data for the science and technology promotion fund...
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