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With scaling of process technologies and increase in process variations, embedded memories will be inherently unreliable. In this paper, we propose redundancy-free adaptive error-correcting codes for the noisy min-sum decoder subject to memory errors. We consider the popular memory error model with a binary symmetric channel. We first revisit the density evolution analysis proposed by Balatsoukas-Stimming...
A very simple coding scheme, called multi-user repetition-aided irregular repeat-accumulate (IRA) code, is proposed to approach the multiple-access channel (MAC) capacity. The main idea is that not only parity checks, which are generated by an IRA encoder, but also repetitions are used in each user's codeword to reduce the coding and decoding complexities. Repetition is a simple way to construct a...
We propose a new class of single error correcting linear codes suitable for a two dimensional hexagonal constellation. The proposed code is a linear subspace of ℤ6n+1n where n is code length and 6n + 1 is a prime number. It corrects a single error in the set |±1, ±αn, ±α2n} where α is a primitive element of ℤ6n+1x. Moreover, we apply the proposed code to a two dimensional hexagonal constellation and...
Consider the problem of reliable multicast over a network in the presence of adversarial errors. In contrast to traditional network error correction codes designed for a given network capacity and a given number of errors, we study an arguably more realistic setting that prior knowledge on the network and adversary parameters is not available. For this setting we propose efficient and throughput-optimal...
The connection between index coding and matroid theory have been well studied in the recent past. El Rouayheb et al. established a connection between multi linear representation of matroids and wireless index coding. Muralidharan and Rajan showed that a vector linear solution to an index coding problem exists if and only if there exists a representable discrete polymatroid satisfying certain conditions...
The connection between index coding and matroid theory have been well studied in the recent past. El Rouayheb et al. established a connection between multi linear representation of matroids and wireless index coding. Muralidharan and Rajan showed that a vector linear solution to an index coding problem exists if and only if there exists a representable discrete polymatroid satisfying certain conditions...
We show that solving a multiple-unicast network coding problem can be reduced to solving a single-unicast network error correction problem, where an adversary may jam at most a single edge in the network. Specifically, we present an efficient reduction that maps a multiple-unicast network coding instance to a network error correction instance while preserving feasibility. The reduction holds for both...
This paper investigates polynomial remainder codes with non-pairwise coprime moduli. We first propose a robust reconstruction for polynomials from erroneous residues when the degrees of all residue errors are small, namely robust Chinese Remainder Theorem (CRT) for polynomials. It basically says that a polynomial can be reconstructed from erroneous residues such that the degree of the reconstruction...
An interpolation-based list decoding algorithm for ℓ-quasi-cyclic codes over finite fields is developed and its guaranteed decoding radius for ℓ-phased burst errors is proven. It is also shown that for this error model and for certain parameter ranges, this new approach is advantageous over existing schemes.
Low density parity check (LDPC) codes with iterative soft decoding have been adopted as the primary error correction coding technology in data storage devices, e.g., hard disk drives (HDDs) and solid state drives (SSDs). Data storage normally has stringent requirements for low probability of decoding failure since there is no re-transmission mechanism as available for most other data communication...
Polar codes are the first error-correcting codes to provably achieve the channel capacity but with infinite code-lengths. For finite codelengths the existing decoder architectures are limited in working frequency by the partial sums computation unit. We explain in this paper how the partial sums computation can be seen as a matrix multiplication. Then, an efficient hardware implementation of this...
As the reliability of NAND Flash memory keeps degrading, Low-Density Parity-Check (LDPC) codes are widely proposed to extend the endurance of Solid State Drive (SSD). However, implementing powerful decoding algorithm such as soft min-sum algorithm with high decoding speed comes along with higher hardware cost. To achieve efficient hardware cost, we propose a multi-strategy ECC scheme which consists...
DRAM industry faces a grand challenge on continuing the scaling of storage node aspect ratio (A/R) to maintain the storage node storage capacitance. One viable option is to intentionally slow down the A/R scaling at the penalty of irreparable weak cells that cannot guarantee target data retention time under worst-case scenarios, and compensate the weak-cell- induced memory errors at the system level...
The reliability of the non-volatile NAND flash memories, measured in terms of Raw Bit Error Rate (RBER), is reaching critical levels for traditional error detection and correction. Therefore, to ensure data trustworthiness in nowadays NAND flash-based Solid State Drives, it becomes essential exploiting powerful correction algorithms such as the Low Density Parity Check (LDPC). However, the burdens...
High bit error rates of next-generation flash devices necessitate the use of more powerful error correction codes (ECCs), such as low-density parity-check (LDPC) codes, instead of the legacy Bose-Chaudhuri-Hocquenghem (BCH) codes. Unlike algebraic codes, the random nature of LDPC codes as well as their ability to use soft information requires the use of Monte Carlo (MC) simulations to evaluate code...
Technology scaling advancement coupled with operational and environmental effects make embedded memories more vulnerable to both manufacturing and transient errors including multi-bit upsets. Conventional error correcting codes incur high latency, area, and power overheads to correct multi-bit errors. In this paper, we propose Embedded Erasure Coding (EEC), a low-cost technique that can correct multi-bit...
Error correcting code (ECC) is an essential method in protection of NAND Flash memories. Complexity of it is increasing rapidly with the increment of error correction capability. Traditionally, the software implementation of ECC which has less cost and high flexibility is nearly ignored due to its inefficiency. This situation can be changed by design of faster software-based ECC scheme. We have found...
In order to make the implementation of the error correcting code(ECC) efficiently, it should be tailored individually to each block, and can be changed over time as the running condition changes. The combined effect of reliability factors makes it difficult to select ECC by considering the effect factors separately. So more appropriate ECC selection method need to be found. Meanwhile, most of the...
Error correcting codes are an unavoidable element in digital communication. Turbo codes are a class of error correcting codes that have been considered for energy constrained wireless communication applications. This paper mainly focuses on the analysis of an efficient turbo encoder in digital communication. The implementation of turbo encoder is performed by using both flip flop and finite state...
Soft errors have been a concern in memory reliability for many years. With device feature size decreasing and memories density increasing, a single event upset (SEU) in memory may generate adjacent bit upsets in a word that may cause data errors. To avoid data errors in memories, Error Correction Codes (ECCs) are used. As multiple bits affected become frequent, the Single Error Correction (SEC) codes...
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