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As modern high performance computing systems have various ICs associated together, one of the most appreciated architecture is direct path passing through the intermediate chips. Inter-chip and intra-chip communication are linked together in this architecture. Therefore to remove crosstalk induced noise and improve signal integrity, a novel CAC and corresponding CODEC which can be applied for both...
Thanks to their ability to store information in a continuous (analog) form, memristors are termed as well-suited for several real-time signal processing tasks. In this context, here we present a memristive circular buffer, using memristor and its multi-bit storage ability to temporarily store encoded information in a compact form, thus improving the area performance as well as the delay and energy...
Satellite communication plays an important role in the ubiquitous global communication. However, for a long time, the communication provided by satellite suffers from serious signal attenuation and transmission delay. Conventional techniques such as HARQ couldn't provide timely service unless powerful channel codes are used. Once channel code fails, retransmission will be inevitable, and unbearable...
State of the art Random Linear Network Coding (RLNC) schemes assume that data streams generate packets with equal sizes. This is an assumption that results in the highest efficiency gains for RLNC. A typical solution for managing unequal packet sizes is to zero-pad the smallest packets. However, the efficiency of this strategy depends heavily on the packet size distribution and can significantly curb...
The article examines the optimal transmission of stochastic processes with delay through the continuous-discrete channels. The extreme properties of optimal coding in terms of information amount maximization are proved.
Network Coding is a packet encoding technique which has recently been shown to improve network performance (by reducing delays and increasing throughput) in broadcast and multicast communications. The cost for such an improvement comes in the form of increased decoding complexity (and thus delay) at the receivers end. Before delivering the file to higher layers, the receiver should first decode those...
In this paper, we address the problem of reducing the completion time of a radio access network to deliver a frame of messages using Rate Aware Instantly Decodable Network Coding (RA-IDNC). While previous works only considered a single base-station setting, this paper extends the results to a more modern paradigm of networks with multiple coordinated basestations. The different rates of the base-stations...
With the rapid growth of content-based network services, there is increasing interest in reducing the emissions associated with brown-energy consumption in Content Delivery Networks (CDNs). At the same time, content needs to be placed in safe Data Center (DC) locations, which are unlikely to be hit by disasters. Further risk reduction is achieved using content replication which provides inter-DC content...
We introduce an optimisation problem to maximise the throughput of class of rateless codes subject to a delay constraint for a point to point erasure packet channel with delayed feedback. We show that this problem is convex. Using the formulation for point to point communication, we extend our approach to the communication of multiple unicast flows in a network.
Consider a radio access network wherein a basestation is required to deliver a set of order-constrained messages to a set of users over independent erasure channels. This paper studies the delivery time reduction problem using instantly decodable network coding (IDNC). Motivated by time-critical and order-constrained applications, the delivery time is defined, at each transmission, as the number of...
Polar codes, introduced by Arikan, achieves the capacity of symmetric channels with “low encoding and decoding complexity” for a large class of underlying channels. Recently, polar code has become the most favourable error correcting code in the viewpoint of information theory due to its property of channel achieving capacity. Although the fully parallel polar code based encoder architecture processes...
Modern wireless systems deal with the adverse and unpredictable channel conditions using two main transmission schemes considered as complimentary: adaptive modulation and coding (AMC) and hybrid ARQ (HARQ). In this work we use the effective capacity as the performance measure to evaluate different design options. We thus show how to calculate this performance measure under independent, identically...
With continuing technology scaling, process variation is increasing and becoming an important cause of memory failure [1]. Most previous memory tests that were developed for delay faults, including GALPAT [2][3][4] and WCGD [3], focus on defects. In this paper we show that a different test strategy is necessary for process variation-induced delay faults (VIDFs) because variations are widespread. In...
We examine lossless data compression from an average delay perspective. An encoder receives input symbols one per unit time from an i.i.d. source and submits binary codewords to a FIFO buffer that transmits bits at a fixed rate to a receiver/decoder. Each input symbol at the encoder is viewed as a status update by the source and the system performance is characterized by the status update age, defined...
This paper focuses Two's complement multipliers with Shortest Bit-size were used without any increase in the delay of the partial product stage. This was done by reducing one row the maximum height of the partial product array generated by a radix-4 Modified Booth multiplier, this reduction may allow for a faster compression of the partial product array and regular layout. By using this method, it...
As per International Technology Roadmap of Semiconductors (ITRS) Network on chip (NoC) becomes suitable example of the integration of several cores on single die. Now a day's die size is continuously growing larger but, at the same time, minimum feature size is continuously shrinking. Although smaller transistor size can result in smaller circuit delay, a smaller feature size for interconnects does...
Register file is the paramount aspect in computer memory unit. Eight bits (one memory unit) results in a single register and 32 of such register make up a register file. In this paper w e have presented the design of a complete register file using reversible logic design. It consists of decoder, multiplexer, memory unit, read and write units. This has been verified using VHDL. In addition to that,...
High-resolution digital-to-analog converters commonly employ segmented architecture. Its application requires thermometric decoder designing. This design process for high resolutions can become a challenge due to decoder complexity. In this paper, common design techniques of a thermometric decoder are discussed in details. The rule to form output logic functions is introduced. The formulas to calculate...
We consider the optimum transmit scheduling problem for a two user energy harvesting cooperative multiple access channel. We assume a slotted model where energy harvests in each slot are known a priori. We propose a delay tolerant cooperation model: the transmitters create common information in a given slot, but need not cooperatively send the created common information immediately; they may relegate...
A swing variable voltage technique (CK-Vdd) is proposed to reduce power consume for generic digital circuit system. The proposed CK-Vdd generates a swing variable voltage, which is different from the conventional constant voltage (Vdd) to the digital circuit. The swing voltage is produced from using Voltage Frequency Adjustor (VFA) and Frequency Duty-Cycle Adjustor (FDCA) circuits. The clock rising...
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