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The Multidimensional Parity Check codes (MDPC) are one of the possible FEC methods of the short information messages. Especially the MDPCs with reduced generator matrix results in codes with block length from few to tens of bits with indispensable code-gain. This paper presents two methods of generation of the MDPC and describe the algorithm for iterative decoding of these codes. The MDPC with short...
Powerful forward error correction codes such as quasi-cyclic low density parity check (QC-LDPC) are required in next-generation coherent optical communication systems [1]. This work describes the design and experimental verification of a high net coding gain (NCG), low complexity QC-LDPC code. Towards this end, we develop a field programmable gate array (FPGA) based platform specially designed for...
Differential encoded LDPC (DE-LDPC) coded systems with multiple symbol differential detection (MSDD) scheme can avoid good estimation of channel state information and compensate performance degradation of differential detection. In this paper, LDPC codes optimization for the DE-LDPC coded systems with MSDD is studied. Simulation results show that the optimized LDPC codes perform much better than the...
In this paper, we provide a simplified perturbation method for LDPC decoding using a binary noise generator with maximal length sequence (m-sequence). The proposed method provides the improved performance of the conventional perturbation-based decoding without performance degradation.
This paper proposes an efficient rateless low-density parity check (LDPC) codes for satellite broadcasting system. The proposed scheme uses the conventional LDPC codes specified in recent digital video broadcasting via satellite (DVB-S) standards, and concatenate them with Luby transform (LT)-like codes in order to form systematic rateless codes. In this way, redundant parities can be made at the...
This paper presents a simple method of designing a protograph-based LDPC codes which has excellent performance with a small number of decoding iterations. In addition to designing LDPC codes based on the iterative decoding threshold as before, we add one more dimension into the design process which is a predefined number of decoding iterations. Simulation results show that the proposed codes have...
A novel self-normalized weighted bit-flipping (SNWBF) decoding algorithm for low-density parity-check (LDPC) codes is proposed. Compared to the best known weighted bit-flipping decoding, the SNWBF algorithm converges significantly faster but with little performance penalty. For decoding of LDPC codes, the proposed SNWBF algorithm considers not only the reliability of the neighboring check nodes, but...
Gradient descent bit-flipping (GDBF) decoding for low-density parity-check (LDPC) codes has gained great attentions because of low complexity and relatively good performance. However, the performance of the GDBF decoding is still much poorer than that of the MS algorithm. To further improve the performance, the iterative decoding process is introduced to GDBF decoding in this paper. At the end of...
The contribution of this paper is implementing a high throughput LDPC codec in FPGA for quantum key distribution (QKD) system. By software, the throughput of error correction in QKD system via LDPC codec could only reach 1.8Mbps, which is not satisfactory for high speed QKD systems. Thus, it is desirable that LDPC error correction is realized in FPGA to increase the throughput. LDPC codec is implemented...
Turbo codes are well known error-correcting codes used in many communication standards. However, they suffer from error floors. Recently, a method - denoted as the flip and check algorithm - that lowers the error floor of turbo codes was proposed. This method relies on the identification of the least reliable bits during the turbo decoding process. Gains of about one order of magnitude were reached...
In this paper, the construction of non binary cyclic One-Step Majority-Logic decoding codes from the dual domain and idempotents is investigated. This had led us to propose a new design algorithm based on Genetic Algorithms, as an extension to previous works on the binary field. With the proposed algorithm, we were able to obtain long new non-binary cyclic OSMLD codes with high coding rates and good...
Non-binary One Step Majority Logic decodable (OSMLD) codes have several advantages over their binary counterparts but unfortunately their decoding complexity is significantly challenging. In this paper, we propose two contributions. Our first contribution is to use the Majority-Logic Decoding (MLGD) algorithm for non-binary cyclic OSMLD codes, since it involves only finite field addition and multiplication,...
This paper investigates the construction and iterative threshold decoding of low rate Quasi-Cyclic One Step Majority logic codes based on combinatorial designs. These codes are constructed with two type of difference family: cyclic disjoint difference sets and cyclic disjoint difference family. They can be encoded with low complexity, and perform very well when decoded with the Iterative threshold...
LDPC code is a powerful error correcting code used in many communication systems. Efficient decoding algorithm and hardware implementation of LDPC code is an important issue. The paper proposes an improved version of the Normalized Min-Sum (NMS) decoding algorithm named “Girth-Aware NMS”. The principle of the GA-NMS is to determine “offline” the optimal normalisation factor of the extrinsic message...
We show that a joint iterative detection and decoding algorithm with spatially-coupled (SC) LDPC codes achieves excellent performance in 100Gbps 16-QAM optical systems with high phase noise. We also demonstrate that complexity and latency of JIDD can be significantly reduced by using SC-LDPC.
A previous study shows that a low-density parity-check (LDPC) coded modulation scheme with an extremely sparse parity-check matrix and non-Gray mapping is able to achieve an error-rate performance compatible to that of a conventional Gray-mapping based scheme. This paper presents an associated iterative demodulation and decoding (IDD) receiver architecture that is targeted at flash memory applications...
This paper investigates the detection schemes for single-carrier underwater acoustic communications over the severe time-dispersive channels. A low-density parity-check (LDPC) code is employed for the improvement of the equalization performance. A detection scheme with Turbo conception is proposed which includes a LDPC decoder in the feedback loop of an iterative block decision feedback equalizer...
For finite coupling lengths, terminated spatially coupled low-density parity-check (SC-LDPC) codes show a non-negligible rate-loss. In this paper, we investigate if this rate loss can be mitigated by tail-biting SC-LDPC codes in conjunction with iterative demapping of higher order modulation formats. Therefore, we examine the BP threshold of different coupled and uncoupled ensembles. A comparison...
In this paper, we study the block error rate (BLER) performance of spatially coupled low-density parity-check (SC-LDPC) codes using a sliding window decoder suited for streaming applications. Previous studies of SC-LDPC have focused on the bit error rate (BER) performance or the frame error rate (FER) performance over the entire length of the code. Here, we consider protograph-based constructions...
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