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High-dynamic-range (HDR) technology allows capturing of video content at a wider range of luminance than low-dynamic-range (LDR) video. The resulting video more closely resembles the scene as perceived by the human eye. However, displays currently support only a limited range of HDR. Therefore, both an HDR version and LDR version of a video should be encoded during content acquisition. This means...
In this paper we show that a small amount of bit stream features can be used to accurately estimate the energy consumption of state-of-the-art software and hardware accelerated decoder implementations for four different video codecs. By testing the estimation performance on HEVC, H.264, H.263, and VP9 we show that the proposed model can be used for any hybrid video codec. We test our approach on a...
This paper proposes a decoder-side intra mode derivation algorithm for block-based video coding. Instead of explicitly coding intra mode, the algorithm derives intra mode at both encoder and decoder using a template-based method. Based on rate-distortion optimization, the encoder locally determines whether intra mode derivation or intra mode explicit coding is used. Further, as no intra mode is coded,...
Today, several predictive video coding standards including MPEG2, MPEG4, H.264, VC1, DivX, VP6 and VP8 do exists. By design, the decoder is typically 10× lower complex than encoder. There are certain classes of emerging applications and services including mobile video, wireless camera, wireless low power surveillance, mobile document scanner and disposable video cameras, which demands lower complexity...
The adoption of HLS has been driven by the need to tackle growing verification costs in traditional RTL design flows. This paper presents an overview of design, optimization and verification using HLS. It also outlines some of the requirements for HLS design to fit into existing design and verification flows and ways in which such flows might be adapted as HLS is more widely deployed.
A multi-mode QC-LDPC decoder is proposed to satisfy the 802.11n/ac WiFi standard. With code-specific design, the overall performance of the decoder is enhanced while ensuring an on-the-fly reconfigurable ability. The proposed architecture has been synthesized using an FPGA for measurements. A state-of-art error rate and implementation complexity are reported. Meanwhile, the throughput has been increased...
As a 3D video extension of Audio Video Coding Standard (AVS), 3D-AVS is being developed to improve the coding efficiency of multi-view video. Since multi-view video is composed of projections of the same scenery from different viewpoints at the same time instant, it contains a large amount of inter-view redundancies. To exploit the inter-view correlation, this paper presents a method to derive the...
Depth-based 3D formats for state of the art High Efficiency Video Coding standard facilitate the synthesis of virtual views with a brief binary representation. Depth maps coding error results in synthesis artefacts for virtual views rendered during Depth Image Based Rendering (DIBR) process. Based on depth maps distortion, synthesized view distortion estimation models are integrated in 3D-High Efficiency...
Scatter-gather direct memory access (DMA) transfers can be used to efficiently fetch graph memory data for onchip processing of graph applications. We present a hardware controlled graph DMA engine which can operate autonomously without the need for CPU interaction. Graph processing algorithms can asynchronously request graph data which is fetched from memory and streamed to the processing core. An...
Video object recognition is an importance topic in both defense and civilian applications. However, object recognition guarantee is not considered in current video coding standard H.264. For this issue, experiments based on H.264/AVC codec are designed to measure the affection of coding parameters on recognition performance. The quantitative functions of recognition performance with coding rate and...
This paper presents an LDPC decoder employing a column-parallel architecture that enables low-power and high-speed operation suitable for the 802.11ad standard. As compared to the conventional row-parallel architecture, the proposed architecture reduces the required memory size by 60% and also minimizes the number of pipeline stages for high throughput operation. Fabricated in 40nm LP CMOS technology,...
The inter prediction decoding is one of the most time consuming modules in modern video decoders, which may significantly limit their real-time capabilities. To circumvent this issue, an efficient acceleration of the HEVC inter prediction decoding module is proposed, by offloading the involved workload to GPU devices. The proposed approach aims at efficiently exploiting the GPU resources by carefully...
Encoded video bitstream is subjected to quality degradation when transmitted over unreliable network. Therefore, a novel feedback-based intra refresh method for robust video coding is proposed in this paper, which takes error concealment's effect, actual loss condition, and the structure of feedback into account. In the decoder, the error correction priority is calculated to reflect the error degree...
Narrowband cyclostationary interference severely limits the performance of power line communications (PLC) on low-voltage in the [3–500] kHz frequency band. For the IEEE 1901.2 narrowband PLC standard system parameters, this interference is not sparse in the time or the frequency domains making recently-proposed sparse interference mitigation techniques ineffective. In this paper, we investigate other...
This work presents an area efficient half row partially parallel pipelined LDPC decoder architecture for IEEE 802.11ad standard. It provides better area and throughput tradeoff by overcoming the low throughput bottleneck in conventional half row decoders and high complexity bottleneck in fully parallel decoders. The proposed architecture is implemented using 40-nm CMOS technology. The proposed half-row...
The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of transformation towards 5G. An energy efficient 18Gbps LDPC decoder based on LDPC ASIP with half layer paralleled architecture is proposed. The feasibility of the design is proven by its demonstrator silicon in 28nm CMOS technology, with a record energy efficiency of 18.4 pJ/decoded bit and area efficiency...
DVB-T2 (digital video broadcasting - second generation terrestrial) is considered as the most advanced digital terrestrial television system. It supports either or any combination of SD (standard definition), HD (high definition) UHD (ultra-high definition), and mobile TV. One of the challenges of the DVB-T2 is the many options it provides in system mode and parameters which needs to be accurately...
The article presents structural logic schemes of building decision support systems in crisis situations with providing support for video conferencing based on heterogeneous networks. The proposed structural solutions allow implementing them with the use of any data transmission systems of the conditions of implementation of new compression technology based on the presented methods and models of adaptive...
In several problems in network information theory, it is important to jointly decode the codewords transmitted by several encoders. For ensembles of i.i.d. random codes, such joint decoding can be analyzed directly with standard methods. In this paper, we develop a general framework to analyze joint decoding for ensembles of random linear codes and ensembles of nested linear codes. The technical difficulty...
A friendly eavesdropper assists communication in a broadcast scenario in which one transmitter wishes to send a common message to two receivers in the presence of a malicious jammer. The jammer attempts to disrupt communication by transmitting a high power Gaussian signal, whereas the friendly eavesdropper ‘hears’ the jammer's transmission and sends an assisting signal to the destinations over an...
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