The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Power control policies in the fading multiple-access channels (MAC) with quality of service (QoS) constraints and random arrivals are studied. Perfect channel side information (CSI) is assumed to be available at both the transmitters and the receiver. Two types of Markovian sources, namely discrete Markov source and Markov fluid source, are considered. The maximum average arrival rates that can be...
Ambient noise not only influences the data transmission but also causes incorrect CSI. To overcome the low SNR problem, traditional methods usually retransmit the same packet for enough times to increase the SNR. Unfortunately, recently works only focus on the failed data retransmission, yet totally overlook the incorrect channel estimation, which are not efficient for multi-user MIMO WLAN. As long...
The recently approved IEEE 802.11ac WLAN standard has dramatically boosted Wi-Fi capabilities through supporting more data streams, larger bandwidth and more efficient frame-aggregation, leading to significantly higher data rates. The multitude of data rates and MIMO configurations to choose from has made it crucial to develop efficient algorithms for rate adaptation and MIMO mode selection (spatial...
UHF EPC Gen2 RFID systems use Dynamic Frame Slotted ALOHA (DFSA) to manage reading of multiple RFID tags. In DFSA, the reader may receive short address messages (RN16) from one or more tags at any given timeslot. To enable RFID readers to read a significantly large population of tags within a small time interval, it is required to increase the underlying throughput by maximizing the percentage of...
Automatic repeat request (ARQ) is widely used in modern communication systems to improve transmission reliability. In conventional ARQ protocols developed for systems with energy-unconstrained receivers, an acknowledgement/negative-acknowledgement (ACK/NACK) message is fed back when decoding succeeds/fails. Such kind of non-adaptive feedback consumes significant amount of energy, and thus will limit...
This paper presents power and execution time efficient implementation of highly adaptive lossless image compression method based on predictor classification and blending, denoted as CBPC coder. Power efficiency is becoming increasingly important in both: datacenters and consumer electronics. This is why we aimed to target its optimization, as well as throughput, of CBPC coder on a CPU and a GPU, using...
Implementation of Quasi-Cyclic (QC) Low Density Parity-Check (LDPC) decoder on FPGA devices has shown great interest in both wireless communication, as well as error correction for Flash memories. This paper presents an FPGA flooded LDPC decoder which uses multiple codeword processing for efficient memory utilization. It is based on a partially parallel implementation, which relies on memory blocks...
In this paper, we study optimal resource allocation strategies for simultaneous information and power transfer (SWIPT) focusing on the system energy efficiency. We consider two-user multiple access channels in which energy harvesting (EH) and information decoding (ID) nodes are spatially separated. We formulate optimization problems that maximize system energy efficiency while taking harvested energy...
We present in this paper a MAC layer protocol capable to cope with lossy links in interference-prone wireless environments. Our approach exploits the recent advances in information theory and physical layer coding by relaying at intermediate nodes corrupted messages. To do so, we rely on collaboration between nodes and on a complete rethinking of the header structures and wireless access techniques...
The performance of uplink HARQ in a Cloud-Radio Access Network (C-RAN) architecture is limited by the two-way latency on the fronthaul links connecting the Remote Radio Heads (RRHs) with the Baseband Unit (BBU) that performs decoding. In order to alleviate this problem, this work considers an alternative architecture based on the separation of control and data planes, in which the control plane is...
8K Ultra HD is being promoted as the next-generation digital video format. From a communication channel perspective, the latest high-efficiency video coding standard (H.265/HEVC) greatly enhances the feasibility of 8K by doubling the compression ratio. Implementation of such codecs is a challenge, owing to ultra-high throughput requirements and increased complexity per pixel. The former corresponds...
A multi-mode QC-LDPC decoder is proposed to satisfy the 802.11n/ac WiFi standard. With code-specific design, the overall performance of the decoder is enhanced while ensuring an on-the-fly reconfigurable ability. The proposed architecture has been synthesized using an FPGA for measurements. A state-of-art error rate and implementation complexity are reported. Meanwhile, the throughput has been increased...
In a timestamp-base packet scheduler, which is an important part of Quality of Service (QoS) enabled network systems, Tag Sorting is the most critical step. This paper presents a high throughput pipelined architecture for Tag Sorting targeting FPGA technology. Our implementation results on Xilinx Virtex II pro 50 chip have shown that our design can run at a maximum clock frequency of 216 MHz and process...
With the rapid increase of the network bandwidth, to process high throughput regular expressions with hardware has become inevitable. This paper presents a novel NFA-based algorithm. In this paper, two theorems were proved and were used to prove the correctness of the algorithm. Our approach was based on three basic modules to construct NFA that can be easily reused in a FPGA or ASIC. The quantitative...
This paper deals with the application of H-ARQ techniques to reliable end-to-end data communications with adaptive adjustment of parameters according to the type of business in aerospace information network, whose applications have to cope with accurate Quality-of-Service (QoS) requirements. In the adaptive H-ARQ strategy, we adopt cell-level RS code as Forward Error Correction (FEC) coding scheme...
Turbo code has been one of the important subjects in coding theory since 1993. This code has low Bit Error Rate (BER) but decoding complexity and delay are big challenges. On the other hand, considering the complexity and delay of separate blocks for coding and encryption, if these processes are combined, the security and reliability of communication system are guaranteed. In this paper a secure decoding...
This paper presents a new innovation network architecture for the analytical model by the integration which challenges both fountain code and Markov chain modeling to improve the throughput performance for ideal channel conditions. In this context, the collision result in corrupted packets and the following MAC layer retransmissions consume extra energy. Channel contention is a serious problem in...
With the tremendous development of mobile Internet and big data, much attention has been attracted on streaming data transmission. In this paper, we propose a quasi real-time transmission scheme using spatially coupled LDPC codes for forward error correction. Recursive encoder and sliding-window decoder with low-latency and low-complexity are employed for data transmission. When any error is reported,...
This paper proposes a CABAC decoder for HEVC that achieves constant high throughput multi-bin decoding with the parallel syntax element parser to solve the dependency problem in the traditional prediction based multi-bin architecture. The hardware implementation with TSMC 90nm CMOS technology can process 1 bins per cycles with 48,430 gate count (270Mbins/sec,) or 3 bins per cycle with 209,422 gate...
This work presents an area efficient half row partially parallel pipelined LDPC decoder architecture for IEEE 802.11ad standard. It provides better area and throughput tradeoff by overcoming the low throughput bottleneck in conventional half row decoders and high complexity bottleneck in fully parallel decoders. The proposed architecture is implemented using 40-nm CMOS technology. The proposed half-row...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.