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The Pauli frame mechanism allows Pauli gates to be tracked in classical electronics and can relax the timing constraints for error syndrome measurement and error decoding. When building a quantum computer, such a mechanism may be beneficial, and the goal of this paper is not only to study the working principles of a Pauli frame but also to quantify its potential effect on the logical error rate. To...
This paper proposes an area efficient and low power Reed-Solomon (RS) decoder. The proposed decoder is designed using eight stage arithmetic pipelined architecture. The pipelined architecture of RS decoder performs the detection of error locator from the input stream and computes the error magnitude polynomial using the Berleykamp Massey's algorithm. The evaluation of error locator and computation...
The VLSI architecture for the low power combined FM0 and Manchester encoder (SOLS) circuit using modified GDI has been proposed in this paper. Comparisons are made with existing architecture using general CMOS Logic. The power consumption and delay in this circuit are reduced. The working conditions for existing circuit for FMO/Manchester encoder and decoder using HCPM technique have also been modified...
In this paper, we propose a novel two-stream framework based on combinational deep neural networks. The framework is mainly composed of two components: one is a parallel two-stream encoding component which learns video encoding from multiple sources using 3D convolutional neural networks and the other is a long-short-term-memory (LSTM)-based decoding language model which transfers the input encoded...
We propose a max-pooling based loss function for training Long Short-Term Memory (LSTM) networks for small-footprint keyword spotting (KWS), with low CPU, memory, and latency requirements. The max-pooling loss training can be further guided by initializing with a cross-entropy loss trained network. A posterior smoothing based evaluation approach is employed to measure keyword spotting performance...
In recent years, machine-to-machine (M2M) networks are widely considered in wireless communication system. Machines typically have constrained power, and their processing and communication capabilities are limited. To avoid the transmission of redundant information to improve the data rate, compressive sensing is a promising tool to be considered. Compressive sensing (CS) is especially useful for...
Encouraged by recent waves of successful applications of deep learning, some researchers have demonstrated the effectiveness of applying convolutional neural networks (CNN) to time series classification problems. However, CNN and other traditional methods require the input data to be of the same dimension which prevents its direct application on data of various lengths and multi-channel time series...
Ternary logic is a promising alternative to conventional binary logic. Implementation of ternary logic circuits however requires devices with multiple thresholds, which is a complex task with current CMOS technology. Carbon Nanotube based FETs (CNFETs) present an easier alternative for the implementation of ternary logic circuits since their threshold voltages can be varied by varying the diameter...
The conventional NOR-based decoders are one ofthe fastest dynamic decoder circuits employed in microprocessors. However, they suffer from a huge amount of power dissipationresulting from the presence of short circuit paths betweenthe supply and the ground through pull-down network. Twodecoder designs with a novel selective precharge circuit have beenproposed in this paper using 32nm FinFET technology...
Convolutional coding system is second-hand for consistent data broadcast. Viterbi decoder is used to decrypt the data at the acceptor end. In Viterbi decoder additional time consuming block is Add Compare and Selection Unit which works on Branch metric and path metric values. In previous work gate level simulation is done for ACSU with Carry look ahead adder. In this paper the ACSU unit is designed...
Logical elements with Single-Event Transients Compensation were simulated on the base of the bulk 28-nm CMOS design rule. The result of an impact of a single nuclear particle on MOS logical gate is a noise pulse, being a single-event transient. The combinational logic of error decoder can prevent all noise pulse propagating through NAND and NOR gates for the output state null “0” of bits error decoder...
The presented paper is based on a new technology, QCA (Quantum-dot Cellular Automata), a promising successor for CMOS transistor technology. The implementation of logic circuits by the traditional devices (eg. transistors, diodes and resistors are replaced by quantum devices (quantum dots or single domain nano magnets). The use of quantum-dots is a promising emerging technology for implementing digital...
A new approach for a battery-less 915MHz ISM band wake-up receiver with digital decoder for wireless sensor network is designed and presented. The proposed receiver architecture is based on a differential rectifier with gate-driver circuit using an ON-OFF Keying modulation for the input signal. To enhance the power conversion efficiency (PCE) of the rectifier for the low input power level, appropriate...
Emerging Memories (EMs) could benefit from ErrorCorrecting Codes (ECCs) able to correct few errors in a fewnanoseconds. The low latency is necessary to meet the DRAM-likeand/or eXecuted-in-Place requirements of Storage Class Memorydevices. In this paper we design an ECC decoder of a shortenedBCH code with 256-data-bit page able to correct three errorsin less than 3 ns. The tight latency constraint...
In-situ timing error detection and correction mechanisms (such as Razor) monitor the performance of actual datapaths, and are believed more resilient in adaptive voltage scaling (AVS) systems, especially when considering local variations. However, Razor has serious hold time problems, of which the overwhelming buffer padding makes it infeasible in advanced process technologies. Pre-error (or in-situ...
BiCMOS technology is necessary to develop a large capacity SRAM with a high operating speed approximating that of a bipolar ECL RAM. Conventional BiCMOS circuits(1) can not obtain high speed operation as bipolar circuits, because the logic swing and circuit stages are large. However, using conventional bipolar circuits for the SRAM peripheral circuits results in large power dissipation. In this paper,...
We realized an all-optical digital physical-layer network coding in Fiber-Wireless networks by employing two SOA-MZI XOR gates. Encoding and decoding operations are demonstrated for 1Gb/s data on 10GHz subcarrier and extended to 60GHz with simulations.
The rising complexity of embedded digital applications and the growing importance of time-to-market require powerful modeling methods and tools to automate the design and implementation process. Electronic design automation (EDA) tools provide the required assistance to every design team, increasing its efficiency and helping meet the hard time to market constraints. Encoders and decoders are an essential...
Visual context is fundamental to understand human actions in videos. However, to efficiently employ temporal context information presents an enormous challenge to this area. Two main problems are long-standing: (1) video frames are redundant while discriminative information is sparse; (2) large amount of interference information is mixed in frame sequences. These factors results in redundant computation...
In this paper, we analyze the performance of various sequence to sequence neural networks on the task of grapheme to phoneme (G2P) conversion. G2P is a very important component in applications like text-to-speech, automatic speech recognition etc,. Because the number of graphemes that a word consists of and the corresponding number of phonemes are different, they are first aligned and then mapped...
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